NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 75

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

4.1.1.3.
Datasheet
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System Management Mode (SMM) Memory Range
The GMCH supports the use of main memory as System Management RAM (SMRAM), enabling the use
of System Management Mode. The GMCH supports two SMRAM options: Compatible SMRAM
(C_SMRAM) and Extended SMRAM (E_SMRAM). System Management RAM (SMRAM) space
provides a memory area that is available for the SMI handler's and code and data storage. This memory
resource is normally hidden from the system OS so that the processor has immediate access to this
memory space upon entry to SMM. The GMCH provides three SMRAM options:
Refer to the Power Management section for more details on SMRAM support.
• APIC Configuration Space (FEC0_0000h–FECF_FFFFh, FEE0_0000h–FEEF_FFFFh). This
• High BIOS Area (FFE0_0000h–FFFF_FFFFh). The top 2 MB of the Extended Memory Region
• Optional HSEG. This Extended SMRAM Address Range, if enabled via the SMRAM register,
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range is reserved for APIC configuration space that includes the default I/O APIC configuration
space. The default Local APIC configuration space is FEE0_0000h to FEEF_0FFFh.
Processor accesses to the Local APIC configuration space do not result in external bus activity since
the Local APIC configuration space is internal to the processor. However, a MTRR must be
programmed to make the Local APIC range uncacheable (UC). The Local APIC base address in
each processor should be relocated to the FEC0_0000h (4GB–20MB) to FECF_FFFFh range so
that one MTRR can be programmed to 64 KB for the Local and I/O APICs. The I/O APIC(s)
usually reside in the I/O Bridge portion of the chipset or as a stand-alone component(s).
I/O APIC units will be located beginning at the default address FEC0_0000h. The first I/O APIC is
located at FEC0_0000h. Each I/O APIC unit is located at FEC0_x000h where x is I/O APIC unit
number 0 through F(hex). This address range will be normally mapped via hub interface to PCI.
The address range between the APIC configuration space and the High BIOS (FED0_0000h to
FEDF_FFFFh) is always mapped to PCI (via the hub interface).
is reserved for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the
system BIOS. Processor begins execution from the High BIOS after reset. This region is mapped to
PCI (via the hub interface) so that the upper subset of this region aliases to 16 MB–256 KB range.
The actual address space required for the BIOS is less than 2 MB but the minimum processor
MTRR range for this region is 2 MB so that full 2 MB must be considered. The ICH supports a
maximum of 1 MB in the High BIOS range.
occupies the range from FEEA_0000h to FEEB_FFFFh. Maps to A0000h–BFFFFh when enabled.
Below 1 MB option that supports compatible SMI handlers.
Above 1 MB option that allows new SMI handlers to execute with write-back cacheable
SMRAM.
Optional larger write-back cacheable T_SEG area of either 512 KB or 1MB in size above 1 MB
that is reserved from the highest area in system DRAM memory. The above 1 MB solutions
require changes to compatible SMRAM handlers code to properly execute above 1 MB.
Intel
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82810E (GMCH)
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