NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 82

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
4.3.1.1.
4.3.1.2.
82
Table 11. Sample Of Possible Mix And Match Options For 4 Row/2 DIMM Configurations
®
82810E (GMCH)
NOTES:
Configuration Mechanism For DIMMs
Detection of the type of DRAM installed on the DIMM is supported via Serial Presence Detect
mechanism as defined in the JEDEC 168-pin DIMM standard. This standard uses the SCL, SDA and
SA[2:0] pins on the DIMMs to detect the type and size of the installed DIMMs. No special
programmable modes are provided on the GMCH for detecting the size and type of memory installed.
Type and size detection must be done via the serial presence detection pins. Use of Serial Presence
Detection is required.
Memory Detection and Initialization
Before any cycles to the memory interface can be supported, the GMCH DRAM registers must be
initialized. The GMCH must be configured for operation with the installed memory types. Detection of
memory type and size is done via the System Management Bus (SMBus) interface on the ICH. This
2-wire bus is used to extract the DRAM type and size information from the serial presence detect port on
the DRAM DIMM modules.
DRAM DIMM modules contain a 5 pin serial presence detect interface, including SCL (serial clock),
SDA (serial data) and SA[2:0]. Devices on the SMBus bus have a seven bit address. For the DRAM
DIMM modules, the upper four bits are fixed at 1010. The lower three bits are strapped on the SA[2:0]
pins. SCL and SDA are connected directly to the System Management Bus on the ICH. Thus data is read
from the Serial Presence Detect port on the DRAM DIMM modules via a series of IO cycles to the ICH.
BIOS essentially needs to determine the size and type of memory used for each of the four rows of
memory in order to properly configure the GMCH system memory interface.
SMBus Configuration and Access of the Serial Presence Detect Ports
For more details on this see the Intel
datasheet.
DRAM Register Programming
This section provides an overview of how the required information for programming the DRAM registers
is obtained from the Serial Presence Detect ports on the DIMMs. The Serial Presence Detect ports are
used to determine Refresh Rate, MA and MD Buffer Strength, Row Type (on a row by row basis),
SDRAM Timings, Row Sizes and Row Page Sizes. Table 12 lists a subset of the data available through
the on-board Serial Presence Detect ROM on each DIMM module.
0
4x(4Mx16) + 2x(2Mx32) D
4x(4Mx16) S
8x(8Mx8) + 4x(4Mx16) D
8x(8Mx8) D
8x(8Mx8) D
4x (4M x16 ) S
1. "S" denotes single-sided DIMM's, "D" denotes double-sided DIMM's.
DIMM0
®
82801AA (ICH) and Intel
0
0
4x(4Mx16) S
0
0
8x(8Mx8) D
4x(4M x 16 ) S
DIMM1
®
82801AB (ICH0) I/O Controller Hub
DRP
CC
0B
70
07
08
77
0C
Total Memory
128 MB
256 MB
32 MB
32 MB
48 MB
64 MB
96 MB
Datasheet
R