NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 19

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

2.2.
Datasheet
R
System Memory Interface Signals
RS[2:0]#
SMAA[11:0]
SMAB[7:4]#
SBS[1:0]
SMD[63:0]
SDQM[7:0]
SCS[3:0]#
SRAS#
SCAS#
SWE#
SCKE[1:0]
Signal Name
Signal Name
I/O
AGTL+
O
CMOS
I/O
CMOS
O
CMOS
O
CMOS
O
CMOS
O
CMOS
O
CMOS
O
CMOS
Type
Type
Response Signals: Indicates type of response as shown below:
RS[2:0]
001
010
011
100
101
110
111
000
Memory Address: SMAA[11:0] and SMAB[7:4]# are used to provide the
multiplexed row and column address to DRAM. SBS[1:0] provide the Bank
Select.
Memory Data: These signals are used to interface to the DRAM data bus.
Input/Output Data Mask: These pins act as synchronized output enables
during read cycles and as a byte enables during write cycles.
Chip Select: For the memory row configured with SDRAM, these pins perform
the function of selecting the particular SDRAM components during the active
state.
SDRAM Row Address Strobe: These signals drive the SDRAM array directly
without any external buffers.
SDRAM Column Address Strobe: These signals drive the SDRAM array
directly without any external buffers.
Write Enable Signal: SWE# is asserted during writes to DRAM.
System Memory Clock Enable: SCKE SDRAM Clock Enable is used to signal
a self-refresh or power-down command to an SDRAM array when entering
system suspend.
Response type
Retry response
Deferred response
Reserved (not driven by the GMCH)
Hard Failure (not driven by the GMCH)
No data response
Implicit Writeback
Normal data response
Idle state
Description
Description
Intel
®
82810E (GMCH)
19