NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 76

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

Intel
4.1.2.
4.1.3.
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82810E (GMCH)
Memory Shadowing
I/O Address Space
Any block of memory that can be designated as read-only or write-only can be “shadowed” into the
GMCH DRAM memory. Typically this is done to allow ROM code to execute more rapidly out of main
DRAM. ROM is used as a read-only during the copy process while DRAM at the same time is
designated write-only. After copying, the DRAM is designated read-only so that ROM is shadowed.
Processor bus transactions are routed accordingly.
The GMCH does not support the existence of any other I/O devices besides itself on the processor bus.
The GMCH generates hub interface bus cycles for all processor I/O accesses that do not target the
Legacy I/O registers supported by the internal Graphics Device. The GMCH contains two internal
registers in the processor I/O space, Configuration Address Register (CONFIG_ADDRESS) and the
Configuration Data Register (CONFIG_DATA). These locations are used to implement PCI
configuration space access mechanism as described in the Registers section of this document.
The processor allows 64K+3 bytes to be addressed within the I/O space. The GMCH propagates the
processor I/O address without any translation to the destination bus and therefore provides addressability
for 64K+3 byte locations. Note that the upper 3 locations can be accessed only during I/O address wrap-
around when processor bus A16# address signal is asserted. A16# is asserted on the processor bus
whenever an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. A16# is also
asserted when an I/O access is made to 2 bytes from address 0FFFFh.
The I/O accesses, other than ones used for PCI configuration space access or ones that target the internal
Graphics Device, are forwarded to hub interface. The GMCH does not post I/O write cycles to IDE.
The GMCH does not respond to I/O cycles initiated on hub interface.
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