NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 61

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

3.5.25.
Datasheet
R
PM_CS—Power Management Control/Status Register
(Device 1)
Address Offset:
Default Value:
Access:
14:13
15
7
12:9
Bits
7:2
1:0
PME Sta
15
(HW=0)
8
PME_Status     R/WC. This bit is 0 to indicate that the GMCH does not support PME# generation
from D3 (cold).
Data Scale (Reserved)     RO. The GMCH does not support data register. This bit always returns 0
when read, write operations have no effect.
Data_Select (Reserved)     RO. The GMCH does not support data register. This bit always returns 0
when read, write operations have no effect.
PME_En    R/W. This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled.
Reserved. Always returns 0 when read, write operations have no effect.
PowerState    R/W. This field indicates the current power state of the GMCH and can be used to set
the GMCH into a new power state. If software attempts to write an unsupported state to this field,
write operation must complete normally on the bus, but the data is discarded and no state change
occurs.
00 = D0
01 = Reserved
10 = Reserved
11 = D3
14
Data Scale (Reserved)
Reserved
13
E0h−E1h
0000h
Read/Write
12
Description
Data_Select (Reserved)
2
1
Intel
9
PowerState
®
82810E (GMCH)
PME En
8
0
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