NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 41

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

3.4.16.
Datasheet
R
DRAMT    DRAM Timing Register (Device 0)
Address Offset:
Default Value:
Access:
Size:
The DRAMT Register controls the operating mode and the timing of the DRAM Controller.
7
7:5
Bit
4
3
2
SDRAM Mode Select
SDRAM Mode Select (SMS). These bits select the operational mode of the GMCH DRAM interface.
The special modes are intended for initialization at power up.
SMS
Note: BIOS must take into consideration SMAB inversion when programming DIMM 2.
DRAM Cycle Time ( DCT ). This bit controls the number of SCLKs for an access cycle.
Bit4
0
1
Intel Reserved.
CAS# Latency (CL). This bit controls the number of CLKs between when a read command is sampled
by the SDRAMs and when the GMCH samples read data from the SDRAMs.
0 = 3 SCLKs (Default)
1 = 2 SCLKs
000
001
010
011
NOP Command Enabled.
All Bank Precharge Enable.
Mode Register Set Enable.
CBR Enable.
Tras
5 SCLKs
6 SCLKs
Trc
7 SCLKs (Default)
8 SCLKs
5
Mode
DRAM in Self-Refresh Mode, Refresh Disabled (Default)
Normal Operation, refresh 15.6usec
Normal Operation, refresh 7.8usec
Reserved
In this mode all processor cyscles to SDRAM result in a NOP Command
on SDRAM interface.
In this mode processor cycles to SDRAM result in an all bank precharge
command on the SDRAM interface.
In this mode all processor cycles to SDRAM result in a mode register
set command on the SDRAM interface. The Command is driven on the
SMAA[11:0] and the SBS[0] lines. SMAA[2:0] must always be driven to
010 for burst of 4 mode. SMAA[3] must be driven to 1 for interleave
wrap type. SMAA[4] needs to be driven to the value programmed in the
CAS# Latency bit. SMAA[6:5] should always be driven to 01.
SMAA[11:7] and SBS[0] must be driven to 000000. BIOS must calculate
and drive the correct host address for each row of memory such that the
correct command is driven on the SMAA[11:0] and SBS[0] lines.
In this mode all processor cycles to SDRAM result in a CBR cycle on
the SDRAM interface.
53h
00h
Read/Write
8 bits
DRAM
Cycle
Time
4
Description
Reserved
Intel
3
Latency
CAS#
2
CAS# Dly
RAS# to
SDRAM
Intel
1
®
82810E (GMCH)
Precharge
SDRAM
RAS#
0
41