NH82810 S L7XK Intel, NH82810 S L7XK Datasheet - Page 73

• Manufacturer Part Number: NH82810 S L7XK
• Manufacturer: Intel

Specifications of NH82810 S L7XK

• Lead Free Status / RoHS Status: Compliant

4.1.1.2.
Datasheet
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Extended Memory Area
This memory area covers the 100000h (1 MB) to FFFFFFFFh (4 GB-1) address range and it is divided
into regions as specified in the following sections.
Main DRAM Address Region (0010_0000h to Top of Main Memory)
The address range from 1 MB to the top of main memory is mapped to main the DRAM address range
controlled by the GMCH. All accesses to addresses within this range, except those listed below, are
forwarded by the GMCH to DRAM.
PCI Memory Address Region (Top of Main Memory to 4 GB)
The address range from the top of main DRAM to 4 GB (top of physical memory space supported by the
GMCH) is normally mapped to PCI (via the hub interface), except for the address ranges listed below.
There are two sub-ranges within the PCI Memory address range defined as APIC Configuration Space
and High BIOS Address Range. The Local Memory Range and the Memory Mapped Range of the
internal Graphics Device MUST NOT overlap with these two ranges.
• Optional ISA Memory Hole (15 MB–16 MB). A 1 MB ISA memory hole in the main DRAM
• TSEG. This Extended SMRAM Address Range, if enabled, occupies the 512 KB or 1 MB range
• Optional Graphics Device Memory. This address range provides either 512KB or 1MB of VGA
• GMCH’s Graphics Controller Status/Control Register Range. A 512 KB space for the graphics
range can be enabled via the FDHC register (Device 0). Note that this memory is not re-mapped.
Accesses to this range are forwarded to PCI (via the hub interface)
below the Top of Main Memory. The size of TSEG is determined by SMRAM[USMM] (Device 0).
When the extended SMRAM space is enabled, non-SMM processor accesses and all other accesses
in this range are forwarded to PCI (via the hub interface). When SMM is enabled, the amount of
memory available to the system is reduced by the TSEG range.
buffer memory for the internal graphics device . If TSEG is enabled, this address range is just below
TSEG. If TSEG is not enabled, the Optional Graphics Device VGA buffer range is just below
TOM. The Graphics Device buffer memory range is enabled and the size selected via
SMRAM[GMS].
controller device’s memory-mapped status/control registers that is requested during Plug and Play.
The base address is programmed in the MMADR PCI Configuration Register for Device 1. Note
that, for legacy support, the VGA registers in the GMCH’s graphics controller are also mapped to
the normal I/O locations.
Intel
®
82810E (GMCH)
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