ATmega16U2 Atmel Corporation, ATmega16U2 Datasheet - Page 127

• Manufacturer Part Number: ATmega16U2
• Manufacturer: Atmel Corporation

Specifications of ATmega16U2

• Flash (kbytes): 16 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 22
• Ext Interrupts: 21
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

16.10 Timer/Counter Timing Diagrams
7799D–AVR–11/10
Using the ICRn Register for defining TOP works well when using fixed TOP values. By using
ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However,
if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as
TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-
forms on the OCnx pins. Setting the COMnx[1:0] bits to two will produce a non-inverted PWM
and an inverted PWM output can be generated by setting the COMnx1:0 to three (See
3 on page
the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clear-
ing) the OCnx Register at the compare match between OCRnx and TCNTn when the counter
increments, and clearing (or setting) the OCnx Register at compare match between OCRnx and
TCNTn when the counter decrements. The PWM frequency for the output when using phase
and frequency correct PWM can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A
is used to define the TOP value (WGM1[3:0] = 9) and COM1A[1:0] = 1, the OC1A output will tog-
gle with a 50% duty cycle.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for
modes utilizing double buffering).
Figure 16-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling
Figure 16-11
TCNTn
OCRnx
OCFnx
(clk
clk
clk
I/O
131). The actual OCnx value will only be visible on the port pin if the data direction for
I/O
Tn
/1)
shows the same timing data, but with the prescaler enabled.
OCRnx - 1
f
OCnxPFCPWM
Figure 16-10
OCRnx
OCRnx Value
shows a timing diagram for the setting of OCFnx.
=
--------------------------- -
2 N TOP
ATmega8U2/16U2/32U2
⋅
f
clk_I/O
⋅
OCRnx + 1
Tn
) is therefore shown as a
OCRnx + 2
Table 16-
127