ATmega16U2 Atmel Corporation, ATmega16U2 Datasheet - Page 202

• Manufacturer Part Number: ATmega16U2
• Manufacturer: Atmel Corporation

Specifications of ATmega16U2

• Flash (kbytes): 16 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 22
• Ext Interrupts: 21
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

21.11.2
21.12 CONTROL endpoint management
21.12.1
7799D–AVR–11/10
STALL handshake and Retry mechanism
Control Write
The Retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the
STALLRQ request bit is set and if there is no retry required.
A SETUP request is always ACK’ed. When a new setup packet is received, the RXSTPI inter-
rupt is triggered (if enabled). The RXOUTI interrupt is not triggered.
The FIFOCON and RWAL fields are irrelevant with CONTROL endpoints. The firmware shall
thus never use them on that endpoints. When read, their value is always 0.
CONTROL endpoints are managed by the following bits:
CONTROL endpoints should not be managed by interrupts, but only by polling the status bits.
The next figure shows a control write transaction. During the status stage, the controller will not
necessary send a NAK at the first IN token:
• RXSTPI is set when a new SETUP is received. It shall be cleared by firmware to
• RXOUTI is set when a new OUT data is received. It shall be cleared by firmware to
• TXINI is set when the bank is ready to accept a new IN packet. It shall be cleared by firmware
• If the firmware knows the exact number of descriptor bytes that must be read, it can then
• or it can read the bytes and poll NAKINI, which tells that all the bytes have been sent by the
USB line
RXSTPI
RXOUTI
TXINI
acknowledge the packet and to clear the endpoint bank.
acknowledge the packet and to clear the endpoint bank.
to send the packet and to clear the endpoint bank.
anticipate on the status stage and send a ZLP for the next IN token,
host, and the transaction is now in the status stage.
SETUP
SETUP
HW
SW
OUT
HW
SW
DATA
ATmega8U2/16U2/32U2
OUT
HW
SW
NAK
IN
STATUS
SW
IN
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