ATmega16U2 Atmel Corporation, ATmega16U2 Datasheet - Page 135
ATmega16U2
Manufacturer Part Number
ATmega16U2
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16U2
Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
22
Ext Interrupts
21
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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16.11.5
16.11.6
16.11.7
16.11.8
16.11.9
7799D–AVR–11/10
OCR1AH and OCR1AL – Output Compare Register 1 A
OCR1BH and OCR1BL – Output Compare Register 1 B
OCR1CH and OCR1CL – Output Compare Register 1 C
ICR1H and ICR1L – Input Capture Register 1
TIMSK1 – Timer/Counter1 Interrupt Mask Register
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OCnx pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers.
IThe Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
Bit
(0x89)
(0x88)
Read/Write
Initial Value
Bit
(0x8B)
(0x8A)
Read/Write
Initial Value
Bit
(0x8D)
(0x8C)
Read/Write
Initial Value
Bit
(0x87)
(0x86)
Read/Write
Initial Value
Bit
(0x6F)
Read/Write
Initial Value
See “Accessing 16-bit Registers” on page 110.
See “Accessing 16-bit Registers” on page 110.
R/W
R/W
R/W
R/W
R
7
0
7
0
7
0
7
0
7
–
0
R/W
R/W
R/W
R/W
R
6
0
6
0
6
0
6
0
6
–
0
ICIE1
R/W
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R/W
R
4
–
0
4
OCR1A[15:8]
0
4
OCR1B[15:8]
0
4
OCR1C[15:8]
0
4
0
OCR1A[7:0]
OCR1B[7:0]
OCR1C[7:0]
ICR1[15:8]
ICR1[7:0]
ATmega8U2/16U2/32U2
OCIE1C
R/W
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
3
0
OCIE1B
R/W
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
2
0
OCIE1A
R/W
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
1
0
TOIE1
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
OCR1AH
OCR1BH
OCR1CH
OCR1AL
OCR1BL
OCR1CL
TIMSK1
ICR1H
ICR1L
135
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