ATmega16U2 Atmel Corporation, ATmega16U2 Datasheet - Page 214

• Manufacturer Part Number: ATmega16U2
• Manufacturer: Atmel Corporation

Specifications of ATmega16U2

• Flash (kbytes): 16 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 22
• Ext Interrupts: 21
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 5
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

21.18.8
21.18.9
21.18.10 UECONX – USB Endpoint Control Register
7799D–AVR–11/10
UENUM – USB Endpoint Number Register
UERST – USB Endpoint Reset Register
• Bits 7:3 – Res: Reserved
These bits are reserved and will always read as zero.
• Bits 2:0 – EPNUM[2:0] Endpoint Number Bits
Writing these bits allows to select the hardware endpoint number that can be accessed by the
CPU interface. This register select the target endpoint number for UECONEX, UECFG0X,
UECFG1X, UESTA0X, UESTA1X, UEINTX, UEIENX, UEDATX, UEBCLX registers. See
point selection” on page 198
• Bits 7:5 – Res: Reserved
These bits are reserved and will always read as zero.
• Bits 4:0 – EPRST[4:0]: Endpoint FIFO Reset Bits
Writing this bit to one keeps the selected endpoint (UENUM register value) under reset state.
selected. Writing this bit to zero completes the endpoint reset operation and makes the endpoint
usable. See
• Bits 7:6 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 5 – STALLRQ: STALL Request Handshake Bit
Writing this bit to one allows the USB controller to generate a STALL answer for the next SETUP
transaction received. This bit is cleared by hardware when the STALL handshake is sent or
when a new SETUP token is received. Writing this bit to zero has no effect. The STALL hand-
shake can be abort using STALLRQC bit.
See
Bit
(0xEB)
Read/Write
Initial Value
Bit
(0xE9)
Read/Write
Initial Value
Bit
(0xEA)
Read/Write
Initial Value
“STALL request” on page 201
“Endpoint reset” on page 197
R
R
7
0
7
0
R
-
-
7
0
-
R
6
0
-
R
R
6
0
6
0
-
-
for more details.
STALLRQ
R/W
R
5
0
-
R
5
0
-
5
0
for more details.
EPRST D4
STALLRQC
R/W
R/W
4
0
R
4
0
for more information.
-
4
0
EPRST D3
RSTDT
ATmega8U2/16U2/32U2
R/W
R/W
3
0
R
3
0
-
3
0
EPRST D2
R/W
R/W
2
0
2
0
R
2
0
-
EPNUM[2:0]
EPRST D1
R/W
R/W
R
1
0
1
0
-
1
0
EPRST D0
EPEN
R/W
R/W
0
0
0
0
R/W
0
0
UECONX
UENUM
UERST
“End-
214