ATmega16U2 Atmel Corporation, ATmega16U2 Datasheet - Page 212
ATmega16U2
Manufacturer Part Number
ATmega16U2
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16U2
Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
22
Ext Interrupts
21
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA16U2
Manufacturer:
ATMEL
Quantity:
853
Company:
Part Number:
ATmega16U2-MU
Manufacturer:
RALINK
Quantity:
2 400
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21.18.4
7799D–AVR–11/10
UDADDR – USB Device Address Register
• Bit 5 – EORSME: End Of Resume Interrupt Enable Bit
Writing this bit to one enables interrupt on EORSMI flag. An end of resume Upstream resume
interrupt will be generated only if the EORSME bit is set to one, the Global Interrupt Flag in
SREG is written to one, and the EORSMI bit is set.
• Bit 4 – WAKEUPE: Wake-up CPU Interrupt Enable Bit
Writing this bit to one enables interrupt on WAKEUPI flag. A wake-up interrupt will be generated
only if the WAKEUPE bit is set to one, the Global Interrupt Flag in SREG is written to one, and
the WAKEUPI bit is set.
• Bit 3 – EORSTE: End Of Reset Interrupt Enable Bit
Writing this bit to one enables interrupt on EORSTI flag. A USB reset interrupt will be generated
only if the EORSTE bit is set to one, the Global Interrupt Flag in SREG is written to one, and the
EORSTI bit is set.
• Bit 2 – SOFE: Start Of Frame Interrupt Enable Bit
Writing this bit to one enables interrupt on SOFI flag. A Start of Frame USB reset interrupt will be
generated only if the SOFE bit is set to one, the Global Interrupt Flag in SREG is written to one,
and the SOFI bit is set.
• Bit 1 – Res: Reserved
This bit is reserved and will always read as zero.
• Bit 0 – SUSPE: Suspend Interrupt Enable Bit
Writing this bit to one enables interrupt on SUSPI flag. A suspend interrupt will be generated
only if the SUSPE bit is set to one, the Global Interrupt Flag in SREG is written to one, and the
SUSPI bit is set.
• Bit 7 – ADDEN: Address Enable Bit
Writing this bit to one will enable the UADD[6:0] field as device address for the USB controller.
When this bit is set the USB device controller will be able to answer all requests on the USB that
refer to the UADD[6:0] USB bus address.
See
• Bits 6:0 – UADD[6:0]: USB Address Bits
These bits contain the USB device address, thatthe USB controller should answer on the USB
bus. This address should be enabled writing one to the ADDEN bit.
Bit
(0xE3)
Read/Write
Initial Value
“Address Setup” on page 199
ADDEN
R/W
7
0
R
6
0
R
5
0
for more details.
R
4
0
UADD[6:0]
ATmega8U2/16U2/32U2
R
3
0
R
2
0
R
1
0
R
0
0
UDADDR
212
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