ATmega16U2 Atmel Corporation, ATmega16U2 Datasheet - Page 40
ATmega16U2
Manufacturer Part Number
ATmega16U2
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16U2
Flash (kbytes)
16 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
22
Ext Interrupts
21
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
5
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA16U2
Manufacturer:
ATMEL
Quantity:
853
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Part Number:
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Manufacturer:
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8.11.6
7799D–AVR–11/10
PLLCSR – PLL Control and Status Register
Table 8-9.
• Bit 7:5 – Res: Reserved Bits
These bits are reserved bits in the ATmega8U2/16U2/32U2 and always read as zero.
• Bit 4 – DIV5 PLL Input Prescaler (1:5)
• Bit 3 – DIV3 PLL Input Prescaler (1:3)
• Bit 2 – PINDIV PLL Input Prescaler (1:1, 1:2)
These bits allow to configure the PLL input prescaler to generate the 8MHz input clock for the
PLL from either a 8 or 16 MHz input.
When using a 8 MHz clock source, this bit must be set to 0 before enabling PLL (1:1).
When using a 16 MHz clock source, this bit must be set to 1 before enabling PLL (1:2).
• Bit 3:2 – Res: Reserved Bits
These bits are reserved and always read as zero.
Bit
0x29 (0x49)
Read/Write
Initial Value
CLKPS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Clock Prescaler Select
R
7
–
0
CLKPS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R
6
–
0
CLKPS1
R
5
–
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DIV5
R/W
4
0
CLKPS0
ATmega8U2/16U2/32U2
DIV3
R
3
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
PINDIV
R
2
0
Clock Division Factor
PLLE
R/W
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PLOCK
128
256
16
32
64
1
2
4
8
R
0
0
PLLCSR
40
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