SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 108

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 15-8. Software Reset
15.3.4.6
108
SRCMP in RSTC_SR
AT91SAM9XE128/256/512 Preliminary
Write RSTC_CR
Watchdog Reset
if PROCRST=1
periph_nreset
if PERRST=1
if EXTRST=1
proc_nreset
(nrst_out)
RSTTYP
NRST
SLCK
MCK
If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field
RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in
RSTTYP.
As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Prog-
ress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left.
No other software reset can be performed while the SRCMP bit is set, and writing any value in
RSTC_CR has no effect.
The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock
cycles.
When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in
WDT_MR:
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a
processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog
Reset, and the Watchdog is enabled by default and with a period set to a maximum.
When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset
controller.
• If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST
• If WDRPROC = 1, only the processor reset is asserted.
line is also asserted, depending on the programming of the field ERSTL. However, the
resulting low level on NRST does not result in a User Reset state.
Freq.
Any
Any
Resynch.
1 cycle
Processor Startup
XXX
= 3 cycles
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
0x3 = Software Reset
6254C–ATARM–22-Jan-10