SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 246

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

24.5.3
Figure 24-4. Read Burst with Boundary Row Access
6254C–ATARM–22-Jan-10
SDRAMC_A[12:0]
D[31:0]
SDWE
SDCS
SDCK
RAS
CAS
Border Management
col a
Row n
col b
Dna
When the memory row boundary has been reached, an automatic page break is inserted. In this
case, the SDRAM controller generates a precharge command, activates the new row and initi-
ates a read or write command. To comply with SDRAM timing parameters, an additional clock
cycle is inserted between the precharge/active (t
mand. This is described in
col c
Dnb
col d
Dnc
Dnd
AT91SAM9XE128/256/512 Preliminary
T
Figure 24-4
RP
= 3
Row m
below.
T
RCD
= 3
RP
col a
) command and the active/read (t
CAS = 2
col b
Dma
col c
Dmb
col d
Dmc
col e
Dmd
RCD
Dme
) com-
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