SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 842

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

46.2.8
46.2.8.1
46.2.8.2
46.2.9
46.2.9.1
46.2.9.2
842
AT91SAM9XE128/256/512 Preliminary
Two-wire Interface (TWI)
USB Host Port (UHP)
TWI: Software Reset
TWI: Overrun in Master Read Mode
UHP: Non-ISO IN transfers
UHP: ISO OUT Transfers
The RXRDY Flag is not reset when a software reset is performed.
None.
When the shift register and the receive holding register (RHR) are full and TWI reads new data,
then an overrun error occurs.
None.
Conditions:
Consider the following sequence:
Consequence: When this defect manifests itself, the Host controller re-attempts the same IN
token.
This problem can be avoided if the system guarantees that the status update can be completed
within the same frame.
Conditions:
Consider the following sequence:
1. The Host controller issues an IN token.
2. The Device provides the IN data in a short packet.
3. The Host controller writes the received data to the system memory.
4. The Host controller is now supposed to carry out two Write transactions (TD status
5. The Host controller raises the request for the first write transaction. By the time the
6. After completing the first write transaction, the Host controller skips the second write
1. The Host controller sends an ISO OUT token after fetching 16 bytes of data from the
2. When the Host controller is sending the ISO OUT data, because of system latencies,
3. While there is an underrun condition, if the Host controller is in the process of bit-stuff-
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
write and TD retirement write) to the system memory in order to complete the status
update.
transaction is completed, a frame boundary is crossed.
transaction.
system memory.
remaining bytes of the packet are not available. This results in a buffer underrun
condition.
ing, it causes the Host controller to hang.
6254C–ATARM–22-Jan-10