SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 50

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

11.3.8
50
AT91SAM9XE128/256/512 Preliminary
ARM Instruction Set Overview
The register r13 is also banked across exception modes to provide each exception handler with
private stack pointer.
The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable
nesting of exceptions.
When an exception has completed, the exception handler must move both the return value in
the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies
according to the type of exception. This action restores both PC and the CPSR.
The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or
remove the requirement for register saving which minimizes the overhead of context switching.
The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be
completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as
invalid, but does not take the exception until the instruction reaches the Execute stage in the
pipeline. If the instruction is not executed, for example because a branch occurs while it is in the
pipeline, the abort does not take place.
The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the
problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction
caused a Prefetch Abort.
A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until
the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for
example because a branch occurs while it is in the pipeline, the breakpoint does not take place.
The ARM instruction set is divided into:
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition
code field (bits[31:28]).
For further details, see the ARM Technical Reference Manual referenced in
43.
1. Preserves the address of the next instruction in the appropriate Link Register that cor-
2. Copies the CPSR into the appropriate SPSR.
3. Forces the CPSR mode bits to a value that depends on the exception.
4. Forces the PC to fetch the next instruction from the relevant exception vector.
• Branch instructions
• Data processing instructions
• Status register transfer instructions
• Load and Store instructions
• Coprocessor instructions
• Exception-generating instructions
responds to the new mode that has been entered. When the exception entry is from:
– ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction
– THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value
into LR (current PC(r15) + 4 or PC + 8 depending on the exception).
(current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the
program to resume from the correct place on return.
Table 11-1 on page
6254C–ATARM–22-Jan-10