SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 841

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

46.2.7.3
46.2.7.4
46.2.7.5
6254C–ATARM–22-Jan-10
SSC: Data sent without any frame synchro
SSC: Last RK Clock Cycle when RK outputs a clock during data transfer
SSC: First RK Clock Cycle when RK outputs a clock during data transfer
Unexpected delay from 2 to 3 system clock cycles is added to TD output. TD should be synchro-
nized on serial clock edge but is actually output a few cycles of SSC clock later.
None.
When SSC is configured with the following conditions:
The data is sent but there is no toggle of the TF line
Transmit STTDLY must be other than 0.
When the SSC receiver is used with the following conditions:
At the end of the data, the RK pin is set in high impedance which might be seen as an unex-
pected clock cycle.
Enable the pull-up on RK pin.
When the SSC receiver is used with the following conditions:
The first clock cycle time generated by the RK pin is equal to MCK /(2 x (value +1)).
None.
• RF is in input,
• TD is synchronized on a receive START (any condition: START field = 2 to 7)
• TF toggles at each start of data transfer
• Transmit STTDLY = 0
• Check TD and TF after a receive START
• the internal clock divider is used (CKS = 0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI = 0)
• RX clock is divided clock (CKS =0 and DIV different from 0)
• RK pin set as output and provides the clock during data transfer (CKO = 2)
• data sampled on RK falling edge (CKI =0)
Problem Fix/Workaround
Problem/Fix Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM9XE128/256/512 Preliminary
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