SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 25

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.1.5.5
8.1.6
8.1.6.1
6254C–ATARM–22-Jan-10
Boot Strategies
Non-volatile Brownout Detector Control
GPNVMBit[3] = 0, Boot on Embedded ROM
Two GPNVM bits are used for controlling the brownout detector (BOD), so that even after a
power loss, the brownout detector operations remain in their state.
Table 8-3
status and the GPNVMBit[3] state at reset.
Table 8-3.
The system always boots at address 0x0. To ensure a maximum number of possibilities for boot,
the memory layout can be configured with two parameters.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This
is done by software once the system has booted. Refer to the section “AT91SAM9XE Bus
Matrix” in the product datasheet for more details.
When REMAP = 0, a non volatile bit stored in Flash memory (GPNVMBit[3]) allows the user to
lay out to 0x0, at his convenience, the ROM or the Flash. Refer to the section “Enhanced
Embedded Flash Controller (EEFC)” in the product datasheet for more details.
Note:
The AT91SAM9XE Matrix manages a boot memory that depends on the value of GPNVMBit[3]
at reset. The internal memory area mapped between address 0x0 and 0x0FFF FFFF is reserved
for this purpose.
If GPNVMBit[3] is set, the boot memory is the internal Flash memory
If GPNVMBit[3] is clear (Flash reset State), the boot memory is the embedded ROM. After a
Flash erase, the boot memory is the internal ROM.
The system boots using the Boot Program.
0x0000 0000
• GPNVMBit[1] is used as a brownout detector enable bit. Setting GPNVMBit[1] enables the
• GPNVMBit[2] is used as a brownout reset enable signal for the reset controller. Setting
• Boot on slow clock (On-chip RC oscillator or 32,768 Hz low-power oscillator)
• Auto baudrate detection
• SAM-BA Boot in case no valid program is detected in external NVM, supporting
BOD, clearing it disables the BOD. Asserting ERASE clears GPNVMBit[1] and thus disables
the brownout detector by default.
GPNVMBit[2] enables the brownout reset when a brownout is detected, clearing
GPNVMBit[2] disables the brownout reset. Asserting ERASE disables the brownout reset by
default.
– Serial communication on a DBGU
– USB Device Port
Memory blocks not affected by these parameters can always be seen at their specified base
addresses. See the complete memory map presented in
summarizes the Internal Memory Mapping for each Master, depending on the Remap
Address
Internal Memory Mapping
AT91SAM9XE128/256/512 Preliminary
REMAP = 0
GPNVMBit[3] clear
ROM
GPNVMBit[3] set
Flash
Figure 8-1 on page
REMAP = 1
SRAM
20.
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