SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 318

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

27.6.5
27.7
27.7.1
6254C–ATARM–22-Jan-10
Divider and PLL Block
Main Oscillator Bypass
PLL Filter
Clock Frequency Register) is set and the counter stops counting. Its value can be read in the
MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of
Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can be
determined.
The user can input a clock on the device instead of connecting a crystal. In this case, the user
has to provide the external clock signal on the XIN pin. The input characteristics of the XIN pin
under these conditions are given in the product electrical characteristics section. The program-
mer has to be sure to set the OSCBYPASS bit to 1 and the MOSCEN bit to 0 in the Main OSC
register (CKGR_MOR) for the external clock to operate properly.
The PLL embeds an input divider to increase the accuracy of the resulting clock signals. How-
ever, the user must respect the PLL minimum input frequency when programming the divider.
Figure 27-5
Figure 27-5. Divider and PLL Block Diagram
The PLL requires connection to an external second-order filter through the PLLRCA and/or PLL-
RCB pin.
MAINCK
Figure 27-6
shows the block diagram of the divider and PLL blocks.
SLCK
shows a schematic of these filters.
AT91SAM9XE128/256/512 Preliminary
Divider B
Divider A
DIVB
DIVA
PLLRCA
MULB
MULA
PLLBCOUNT
PLLACOUNT
Counter
Counter
PLL B
PLL A
PLL B
PLL A
OUTB
OUTA
LOCKB
LOCKA
PLLBCK
PLLACK
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