SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 482

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

T
33.10.5
Name:
Addresses: 0xFFFAC010 (0), 0xFFFD8010 (1)
Access:
Reset Value: 0x00000000
TWI_CWGR is only used in Master mode.
• CLDIV: Clock Low Divider
The SCL low period is defined as follows:
• CHDIV: Clock High Divider
The SCL high period is defined as follows:
T
• CKDIV: Clock Divider
The CKDIV is used to increase both SCL high and low periods.
482
low
high
=
=
31
23
15
(
–
7
(
(
CLDIV
(
CHDIV
AT91SAM9XE128/256/512 Preliminary
TWI Clock Waveform Generator Register
TWI_CWGR
Read-write
×
×
2
CKDIV
2
CKDIV
30
22
14
–
6
)
+
)
+
4 )
4 )
×
×
T
MCK
T
MCK
29
21
13
–
5
28
20
12
–
4
CHDIV
CLDIV
27
19
11
–
3
26
18
10
–
2
CKDIV
25
17
–
9
1
6254C–ATARM–22-Jan-10
24
16
–
8
0