SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 847

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

6254C–ATARM–22-Jan-10
Doc.
Rev
6254B
Comments
Overview:
“Features”,
Debug Unit (DBGU), added “mode for general purpose two-sire UART serial communication“
Section 10.4.9 “Ethernet 10/100
Section 9.13 “Chip
Removed former Section 5.2 “Power Consumption”.
Table 3-1, “Signal Description
PIOA - PIOB -
Section 6. “I/O Line
“Features”,
“Features” “Four Universal Synchronous/Asynchronous Receiver Transmitters
Encoding/Decoding,
Section 1. “AT91SAM9XE128/256/512
Section 6.3 “Shutdown Logic
Debug and Test
Section 12.5 “JTAG Port
Boot Program:
Section 13.4.4 “In-Application Programming (IAP)
AIC:
Section 29.6.3 “Interrupt
Section 29.7.5 “Protect
Qualified/Internal on ATP
DBGU:
Section 30.1
ECC:
Section 25.4.3 “ECC Status Register 1”
MULERRx on bitfields, 2, 18, 22, 26, 30.
Section 25.4.1 “ECC Control
EEFC:
Section 20.4.2 “EEFC Flash Command
ISI:
Section 41.4.7 “ISI Preview
PMC:
Section 28.7 “Programming
RSTC:
Section 15.3.4.5 “Software Reset”
“Ethernet MAC 10/100
“Additional Embedded Memories”
“Description”, added to second paragraph; “...two-pin UART can be used as stand-alone...”
PIOC”, has a foot note added to its comments column. SHDWN is active Low.
Identification”, SAM9XE512 chip ID is 0x329AA3A0.
Considerations”, unneeded paragraphs removed.
Mode”, enabling Debug Control Protect Mode in AIC_DCR register updated.
Sources”, Interrupt Source 1, OR-wiring description updated.
Pins”, added to Debug and Test.
Register”, updated PREV_VSIZE and PREV_HSIZE with RGB only comments
Sequence”, steps 5 and 6: “By default PRES parameter is set to 0.....”
Register”, added new bitfield: SRST
Pins”, updated with external pull-up requirement.
List”, comment column updated in certain instances and
MAC”, 128-byte FIFOs (typo corrected).
PERRST must be used with PROCRST, except for debug purposes.
Base-T”, 128-byte FIFOs (typo corrected).
Description”, 2nd and 3rd paragraphs improved.
Register”, updated FARG bit field description
and
AT91SAM9XE128/256/512 Preliminary
Section 25.4.4 “ECC Status Register
Fast Read Time: 45 ns.
Feature”, added to datasheet.
(USART)”, added Manchester
2”, ECCERRx renamed as
“PIO Controller -
Change
Request
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