SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 447

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

32.7.9
Name:
Addresses:
Access Type:
Note:
• CPOL: Clock Polarity
0 = The inactive state value of SPCK is logic level zero.
1 = The inactive state value of SPCK is logic level one.
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the
required clock/data relationship between master and slave devices.
• NCPHA: Clock Phase
0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.
1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is
used with CPOL to produce the required clock/data relationship between master and slave devices.
• CSAAT: Chip Select Active After Transfer
0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is
requested on a different chip select.
• BITS: Bits Per Transfer (See the
The BITS field determines the number of data bits transferred. Reserved values should not be used.
6254C–ATARM–22-Jan-10
31
23
15
7
SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the trans-
lated value unless the register is written.
SPI Chip Select Register
30
22
14
SPI_CSR0... SPI_CSR3
0xFFFC8030 (0), 0xFFFCC030 (1)
Read/Write
6
BITS
0000
0001
0010
0011
0100
0101
0110
0111
BITS
(Note:)
29
21
13
5
below the register table;
AT91SAM9XE128/256/512 Preliminary
28
20
12
4
DLYBCT
DLYBS
SCBR
CSAAT
Section 32.7.9 “SPI Chip Select Register” on page
27
19
11
3
Bits Per Transfer
26
18
10
–
2
10
11
12
13
14
15
8
9
NCPHA
25
17
9
1
CPOL
24
16
8
0
447.)
447