SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 176

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

22.4.2
22.5
22.5.1
22.6
176
Product Dependencies
Functional Description
AT91SAM9XE128/256/512 Preliminary
Connection Examples
I/O Lines
Figure 22-2
Figure 22-2. EBI Connections to Memory Devices
The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines.
The programmer must first program the PIO controller to assign the External Bus Interface pins
to their peripheral function. If I/O lines of the External Bus Interface are not used by the applica-
tion, they can be used for other purposes by the PIO Controller.
The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the exter-
nal memories or peripheral devices. It controls the waveforms and the parameters of the
external address, data and control buses and is composed of the following elements:
• the Static Memory Controller (SMC)
• the SDRAM Controller (SDRAMC)
EBI
A1/NWR2/NBS2
shows an example of connections between the EBI and external devices.
NWR1/NBS1
NWR3/NBS3
NWR0/NWE
NCS1/SDCS
NRD/NOE
A0/NBS0
A18-A25
A16/BA0
A17/BA1
D0-D31
A2-A15
SDCKE
SDA10
NCS2
NCS3
NCS4
NCS5
SDCK
SDWE
NCS0
RAS
CAS
A0/NWR0/NBS0
NRD/NOE
D0-D7
D16-D23
D0-D7
SDWE
NBS0
SDWE
NBS2
D0-D7
CS
CLK
CKE
WE
RAS
CAS
DQM
D0-D7
CS
CLK
CKE
WE
RAS
CAS
DQM
OE
D0-D7
CS
WE
128K x 8
SRAM
SDRAM
2M x 8
SDRAM
2M x 8
A0-A9, A11
A0-A9, A11
A0-A16
BA0
BA1
BA0
BA1
A10
A10
A2-A11, A13
SDA10
A16/BA0
A17/BA1
A2-A11, A13
SDA10
A16/BA0
A17/BA1
A1-A17
D8-D15
NWR1/NBS1
NRD/NOE
D24-D31
D8-D15
SDWE
SDWE
NBS3
NBS1
D0-D7
CS
OE
WE
128K x 8
CS
CLK
CKE
WE
RAS
CAS
DQM
D0-D7
CS
CLK
CKE
WE
RAS
CAS
DQM
D0-D7
SRAM
SDRAM
2M x 8
SDRAM
2M x 8
A0-A16
A0-A9, A11
A0-A9, A11
BA0
BA1
BA0
BA1
A10
A10
6254C–ATARM–22-Jan-10
A2-A11, A13
SDA10
A16/BA0
A17/BA1
A1-A17
A2-A11, A13
SDA10
A16/BA0
A17/BA1