SAM9XE512 Atmel Corporation, SAM9XE512 Datasheet - Page 672

• Manufacturer Part Number: SAM9XE512
• Manufacturer: Atmel Corporation

Specifications of SAM9XE512

• Flash (kbytes): 512 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 180 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 6
• Ssc: 1
• Ethernet: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 312
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.65 to 1.95
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

38.4.1.3
38.4.1.4
38.4.1.5
38.4.1.6
672
AT91SAM9XE128/256/512 Preliminary
Transmit Buffer List
Address Matching
Interrupts
Transmitting Frames
Transmit data is read from areas of data (the buffers) in system memory These buffers are listed
in another data structure that also resides in main memory. This data structure (Transmit Buffer
Queue) is a sequence of descriptor entries (as defined in
this data structure.
To create this list of buffers:
The EMAC register-pair hash address and the four specific address register-pairs must be writ-
ten with the required values. Each register-pair comprises a bottom register and top register,
with the bottom register being written first. The address matching is disabled for a particular reg-
ister-pair after the bottom-register has been written and re-enabled when the top register is
written.
ister-pair may be written at any time, regardless of whether the receive circuits are enabled or
disabled.
There are
single interrupt. Depending on the overall system design, this may be passed through a further
level of interrupt collection (interrupt controller). On receipt of the interrupt signal, the CPU
enters the interrupt handler (Refer to the AIC programmer datasheet). To ascertain which inter-
rupt has been generated, read the interrupt status register. Note that this register clears itself
when read. At reset, all interrupts are disabled. To enable an interrupt, write to interrupt enable
register with the pertinent interrupt bit set to 1. To disable an interrupt, write to interrupt disable
register with the pertinent interrupt bit set to 1. To check whether an interrupt is enabled or dis-
abled, read interrupt mask register: if the bit is set to 1, the interrupt is disabled.
To set up a frame for transmission:
1. Allocate a number (n) of buffers of between 1 and 2047 bytes of data to be transmitted
2. Allocate an area 2n words for the transmit buffer descriptor entry in system memory
3. If fewer than 1024 buffers are defined, the last descriptor must be marked with the wrap
4. Write address of transmit buffer descriptor entry to EMAC register transmit_buffer
5. The transmit circuits can then be enabled by writing to the network control register.
1. Enable transmit in the network control register.
2. Allocate an area of system memory for transmit data. This does not have to be contigu-
3. Set-up the transmit buffer list.
4. Set the network control register to enable transmission and enable interrupts.
5. Write data for transmission into these buffers.
6. Write the address to transmit buffer descriptor queue pointer.
7. Write control and length to word one of the transmit buffer descriptor entry.
in system memory. Up to 128 buffers per frame are allowed.
and create N entries in this list. Mark all entries in this list as owned by EMAC, i.e. bit 31
of word 1 set to 0.
bit — bit 30 in word 1 set to 1.
queue pointer.
ous, varying byte lengths can be used as long as they conclude on byte borders.
See “Address Checking Block” on page 667.
14
interrupt conditions that are detected within the EMAC. These are ORed to make a
for details of address matching. Each reg-
Table 38-2 on page
6254C–ATARM–22-Jan-10
664) that points to