ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet
ADSP-21364SBBCZENG
Related parts for ADSP-21364SBBCZENG
ADSP-21364SBBCZENG Summary of contents
Page 1
... On-chip memory—3M bit of on-chip SRAM and a dedicated 4M bit of on-chip mask-programmable ROM Code compatible with all other members of the SHARC family The ADSP-21364 is available with a 333 MHz core instruction rate and unique audio centric peripherals such as the Digi- tal Audio Interface, S/PDIF transceiver, serial ports, 8- channel asynchronous sample rate converter, precision clock generators and more ...
Page 2
... ADSP-21364 KEY FEATURES – PROCESSOR CORE At 333 MHz (3.0 ns) core instruction rate, the ADSP-21364 performs 2 GFLOPS/666 MMACS 3M bit on-chip single-ported SRAM (1M Bit in blocks 0 and 1, and 0.50M Bit in blocks 2 and 3) for simultaneous access by core processor and DMA 4M bit on-chip single-ported mask-programmable ROM (2M bit in block 0 and 2M bit in block 1) ...
Page 3
... Many other SRU configura- Speed tions are possible. (at 333 MHz) ADSP-21364 FAMILY CORE ARCHITECTURE The ADSP-21364 is code compatible at the assembly level with 1.5 ns the ADSP-2126x, ADSP-21160 and ADSP-21161, and with the 6.0 ns first generation ADSP-2106x SHARC DSPs. The ADSP-21364 shares architectural features with the ADSP-2126x and 13 ...
Page 4
... Data Address Generators With Zero-Overhead Hardware Circular Buffer Support The ADSP-21364’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient program- ming of delay lines and other data structures required in digital Rev ...
Page 5
... Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-21364 can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetch- ing up to four 32-bit values from memory—all in a single instruction ...
Page 6
... IDP (Input Data Port), the Parallel Data Acquisition Port (PDAP), or the parallel port. Twenty-five channels of DMA are available on the ADSP-21364—two for the SPI interface, two for memory-to-memory transfers, twelve via the serial ports, eight via the Input Data Port, and one via the processor’s parallel port ...
Page 7
... SPI compatible devices, either acting as a master or slave device. The ADSP-21364 SPI compatible peripheral implemen- tation also features programmable baud rate and clock phase and polarities. The ADSP-21364 SPI compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention. ...
Page 8
... ADSP-21364 Timers The ADSP-21364 has a total of four timers: a core timer able to generate periodic software interrupts and three general purpose timers that can generate periodic interrupts and be indepen- dently set to operate in one of three modes: • Pulse Waveform Generation mode • Pulse Width Count /Capture mode • ...
Page 9
... With a full version of VisualDSP++ installed (sold separately), engineers can develop software for the EZ-KIT Lite or any cus- tom defined system. Connecting one of Analog Devices JTAG emulators to the EZ-KIT Lite board enables high-speed, non- intrusive emulation. Rev. PrB | Page September 2004 ADSP-21364 ...
Page 10
... ADSP-21364 ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21364 architecture and functionality. For detailed information on the ADSP-2136x Family core architecture and instruction set, refer to the ADSP-2136x SHARC Processor Hardware Reference and the ADSP-2136x SHARC Processor Programming Reference. Rev. PrB | Page September 2004 ...
Page 11
... Open Drain, and T = Three-State, (pd) = pulldown resistor, (pu) = pullup resistor. . Function Parallel Port Address/Data. The ADSP-21364 parallel port and its corresponding DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode. Each AD pin has a 22.5 kΩ ...
Page 12
... ADSP-21364 SPI interaction, any of the master ADSP-21364's flag pins can be used to drive the SPIDS signal on the ADSP-21364 SPI slave device. SPI Master Out Slave In. If the ADSP-21364 is configured as a master, the MOSI pin becomes a data transmit (output) pin, transmitting output data. If the ADSP-21364 is configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data ...
Page 13
... Three-state is a three-state driver with pullup disabled. Function Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21364 clock input. It configures the ADSP-21364 to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator ...
Page 14
... ADSP-21364 ADDRESS DATA PINS AS FLAGS To use these pins as flags (FLAGS15–0) set (=1) bit 20 of the SYSCTL register to disable the parallel port. Then set (=1) bits the SYSCTL register accordingly. Table 4. AD15–0 to Flag Pin Mapping AD Pin Flag Pin AD Pin AD0 ...
Page 15
... Preliminary Technical Data ADSP-21364 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS 1 Parameter V Internal (Core) Supply Voltage DDINT A Analog (PLL) Supply Voltage VDD V External (I/O) Supply Voltage DDEXT 2 V High Level Input Voltage @ Low Level Input Voltage @ High Level Input Voltage @ V IH_CLKIN ...
Page 16
... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21364 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
Page 17
... Preliminary Technical Data Note the definitions of various clock periods that are a function of CLKIN and the appropriate ratio control Table 8. ADSP-21364 CLKOUT and CCLK Clock Generation Operation Timing Description Requirements CLKIN Input Clock CCLK Core Clock Table 9. Clock Periods 1 Timing Description Requirements ...
Page 18
... ADSP-21364 Power-Up Sequencing The timing requirements for processor startup are given in Table 10. Table 10. Power-Up Sequencing Timing Requirements (Processor Startup) Parameter Timing Requirements t RESET Low Before V RSTVDD Before V IVDDEVDD DDINT 1 t CLKIN Valid After V CLKVDD t CLKIN Valid Before RESET Deasserted CLKRST ...
Page 19
... CKH Figure 7. Clock Input Clock Signals The ADSP-21364 can use an external clock or a crystal. See CLKIN pin description. The programmer can configure the ADSP-21364 to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. the component connections used for a crystal operating in fun- damental mode ...
Page 20
... ADSP-21364 Reset Table 12. Reset Parameter Timing Requirements 1 t RESET Pulse Width Low WRST t RESET Setup Before CLKIN Low SRST Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 µs while RESET is low, assuming 1 stable VDD and CLKIN (not including start-up time of external clock oscillator). ...
Page 21
... Parameter Switching Characteristic t Timer Pulse Width Output PWMO DAI_P20-1 (TIMER2-0) Min 4 × t – 1 PCLK t WCTIM Figure 11. Core Timer Min Max 2 t – 1 2(2 PCLK t PWMO Figure 12. Timer PWM_OUT Timing Rev. PrB | Page September 2004 ADSP-21364 Max Unit ns Unit 31 – PCLK ...
Page 22
... ADSP-21364 Timer WDTH_CAP Timing The following timing specification applies to Timer0, Timer1, and Timer2 in WDTH_CAP (pulse width count and capture) mode. Timer signals are routed to the DAI_P20–1 pins through the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. ...
Page 23
... All Timing Parameters and Switching Characteristics apply to external DAI pins (DAI_P07 – DAI_P20). t STRIG t HTRIG t DPCGIO t DTRIG Figure 15. Precision Clock Generator (Direct Pin Routing) Rev. PrB | Page September 2004 ADSP-21364 Min Max 2.5 10 2.5 + 2.5 × 2.5 × t PCGOW PCGOW 48 ...
Page 24
... ADSP-21364 Flags The timing specifications provided below apply to the FLAG3–0 and DAI_P20–1 pins, the parallel port and the serial peripheral interface (SPI). See Table 3, “Pin Descriptions,” on page 11 more information on flag use. Table 19. Flags Parameter Timing Requirement t FLAG3–0 IN Pulse Width ...
Page 25
... Preliminary Technical Data Memory Read—Parallel Port Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) when the ADSP-21364 is accessing external memory space. Table 20. 8-Bit Memory Read Cycle Parameter Timing Requirements t Address/Data 7–0 Setup Before RD High DRS t Address/Data 7–0 Hold After RD High ...
Page 26
... ADSP-21364 Table 21. 16-bit Memory Read Cycle Parameter Timing Requirements t Address/Data 15–0 Setup Before RD High DRS t Address/Data 15–0 Hold After RD High DRH Switching Characteristics t ALE Pulse Width ALEW 1 t Address/Data 15–0 Setup Before ALE Deasserted ADAS t ALE Deasserted to Read Asserted ALERW t Delay Between RD Rising Edge to Next Falling Edge. ...
Page 27
... Preliminary Technical Data Memory Write—Parallel Port Use these specifications for asynchronous interfacing to memo- ries (and memory-mapped peripherals) when the ADSP-21364 is accessing external memory space. Table 22. 8-bit Memory Write Cycle Parameter Switching Characteristics: t ALE Pulse Width ALEW 1 t Address/Data 15–0 Setup Before ALE Deasserted ...
Page 28
... ADSP-21364 Table 23. 16-bit Memory Write Cycle Parameter Switching Characteristics t ALE Pulse Width ALEW 1 t Address/Data 15–0 Setup Before ALE Deasserted ADAS t ALE Deasserted to Write Asserted ALERW t Write Deasserted to ALE Asserted RWALE t Delay Between WR Rising Edge to next WR Falling Edge WRH 1 t Address/Data 15–0 Hold After ALE Deasserted ...
Page 29
... Referenced to drive edge. Serial port signals (SCLK, FS, DxA,/DxB) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifica- tions provided below are valid at the DAI_P20–1 pins. Rev. PrB | Page September 2004 ADSP-21364 Min Max Unit 2 ...
Page 30
... ADSP-21364 Table 26. Serial Ports—Enable and Three-State Parameter Switching Characteristics 1 t Data Enable from External Transmit SCLK DDTEN 1 t Data Disable from External Transmit SCLK DDTTE 1 t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to drive edge. Table 27. Serial Ports—External Late Frame Sync ...
Page 31
... DAI_P20-1 (FS) t DDTI DAI_P20-1 (DATA CHANNEL A/B) DRIVE EDGE t DDTEN DRIVE EDGE t DDTIN Figure 22. Serial Ports Rev. PrB | Page September 2004 ADSP-21364 DATA RECEIVE— EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t SCLKW t DFSE t t SFSE HOFSE t SDRE DATA TRANSMIT — EXTERNAL CLOCK ...
Page 32
... ADSP-21364 Input Data Port (IDP) The timing requirements for the IDP are given in Signals (SCLK, FS, SDATA) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 28. IDP Parameter Timing Requirements ...
Page 33
... The timing requirements for the PDAP are provided in Table 29. PDAP is the parallel mode operation of channel 0 of the IDP. For details on the operation of the IDP, see the IDP chapter of the ADSP-2136x SHARC Processor Hardware Refer- Table 29. Parallel Data Acquisition Port (PDAP) Parameter Timing Requirements ...
Page 34
... ADSP-21364 Sample Rate Converter—Serial Input Port The SRC input signals (SCLK, FS, and SDATA) are routed from the DAI_P20–1 pins using the SRU. Therefore, the timing spec- ifications provided in Table 30 are valid at the DAI_P20–1 pins. Table 30. SRC, Serial Input Port ...
Page 35
... SCLK. Note that SCLK rising edge is the sampling edge and the falling edge is the drive edge. Min 4 5.5 2 SAMPLE EDGE t SISCLKW t SIFS t SR CTDH t SRCTDD Figure 26. SRC Serial Output Port Timing Rev. PrB | Page September 2004 ADSP-21364 Max Unit SIHFS ...
Page 36
... ADSP-21364 SPDIF Transmitter Serial data input to the SPDIF transmitter can be formatted as 2 left justified right justified with word widths of 16, 18, 20 bits. The following sections provide timing for the transmitter. SPDIF Transmitter—Serial Input Waveforms Figure 27 shows the right-justified mode. LRCLK is HI for the left channel and LO for the right channel ...
Page 37
... TXCLK Frequency for TXCLK = 256 × FS Frame Rate Min 4 5 SAMPLE EDGE t SISCLKW t SISFS t SISD Figure 30. SPDIF Transmitter Input Timing Min Rev. PrB | Page September 2004 ADSP-21364 Max Unit SIHFS t SIH D Max Unit 147.5 MHz 98.4 MHz 73 ...
Page 38
... ADSP-21364 SPDIF Receiver The following sections describe timing as it relates to the SPDIF receiver. Internal Digital PLL Mode In internal Digital Phase-locked Loop mode the internal PLL (Digital PLL) generates the 512 × Fs clock. Table 34. SPDIF Receiver Internal Digital PLL Mode Timing Parameter ...
Page 39
... RIGHT-JUSTIFIED MODE ) MCP t DDS MSB t DDH t DDP t DDS MSB t DDH t DDP Figure 32. SPDIF Receiver External PLL Mode Timing Rev. PrB | Page September 2004 ADSP-21364 Min Max Unit 10 ns 100 MHz 1/2 SCLK Period ns 1/2 SCLK Period ns t DDS LSB ...
Page 40
... ADSP-21364 SPI Interface—Master Table 36. SPI Interface Protocol — Master Switching and Timing Specifications Parameter Timing Requirements t Data Input Valid to SPICLK Edge (Data Input Set-up Time) SSPIDM t SPICLK Last Sampling Edge to Data Input Not Valid HSPIDM Switching Characteristics t Serial Clock Cycle ...
Page 41
... MSB MSB LSB VALID Figure 34. SPI Slave Timing Rev. PrB | Page September 2004 ADSP-21364 Min Max 4 × t PCLK 2 × t PCLK 2 × t – 2 PCLK 2 × t PCLK 2 × t PCLK 2 × ...
Page 42
... ADSP-21364 JTAG Test Access Port and Emulation Table 38. JTAG Test Access Port and Emulation Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP 1 t System Inputs Setup Before TCK Low ...
Page 43
... Preliminary Technical Data OUTPUT DRIVE CURRENTS Figure 36 shows typical I-V characteristics for the output driv- ers of the ADSP-21364. The curves represent the current drive capability of the output drivers as a function of output voltage 3.11V, 125° -10 3.11V, 125° C ...
Page 44
... LOAD CAPACITANCE (pF) Figure 41. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) THERMAL CHARACTERISTICS The ADSP-21364 processor is rated for performance to a maxi- mum junction temperature of 125°C. Table 39 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to-board measure- ment complies with JESD51-8 ...
Page 45
... Airflow = 2 m/s JMA θ JC Ψ Airflow = 0 m/s JT Ψ Airflow = 1 m/s JMT Ψ Airflow = 2 m/s JMT 1 The thermal characteristics values provided in these tables are modeled values. 1 Typical Unit 16.50 °C/W 15.14 °C/W 14.35 °C/W 6.83 °C/W 0.129 °C/W 0.255 °C/W 0.261 °C/W Rev. PrB | Page September 2004 ADSP-21364 ...
Page 46
... ADSP-21364 136-BALL BGA PIN CONFIGURATIONS The following table shows the ADSP-21364’s pin names and their default function after reset (in parentheses). Table 43. 136-Ball Mini-BGA Pin Assignments Pin Name BGA Pin Name Pin# CLKCFG0 A01 CLKCFG1 XTAL A02 GND TMS A03 V DDEXT ...
Page 47
... K14 DAI_P14 (SFS23) P01 P02 P03 P04 P05 P06 P07 P08 P09 P10 P11 P12 P13 P14 Rev. PrB | Page September 2004 ADSP-21364 BGA Pin Name BGA Pin# Pin# L01 AD0 M01 L02 WR M02 L04 GND M03 L05 GND M12 ...
Page 48
... ADSP-21364 Figure 42. 136-Ball Mini-BGA Pin Assignments (Bottom View, Summary KEY V A GND* DDINT VDD V A I/O SIGNALS DDEXT VSS *USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S GROUND PLANE. Rev. PrB | Page September 2004 ...
Page 49
... Preliminary Technical Data 144-LEAD LQFP PIN CONFIGURATIONS The following table shows the ADSP-21364’s pin names and their default function after reset (in parentheses). Table 44. 144-Lead LQFP Pin Assignments Pin Name LQFP Pin Name Pin No DDINT DDINT CLKCFG0 2 GND CLKCFG1 ...
Page 50
... ADSP-21364 PACKAGE DIMENSIONS The ADSP-21364 is available in a 136-ball Mini-BGA package and a 144-lead integrated heatsink LQFP package. 12.00 BSC SQ PIN A1 INDICATOR TOP VIEW 1.70 MAX 1. DIMENSIONS ARE IN MILIMETERS (MM). 2. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0. ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. ...
Page 51
... HEATSLUG IS COINCIDENT TTOM SURFACE AND DOES NOT PROTRUDE BEYOND IT. 144 0.50 1 BSC PIN 1 INDICA TOR TYP (LEAD PITCH DETAIL A Figure 44. 144-Lead Integrated Heatsink LQFP (SQ-144-3) Rev. PrB | Page September 2004 ADSP-21364 22.00 BSC SQ 20. 00 BSC 108 13.71 13.21 DIA 12.71 72 HEATSLUG ON BOTTOM (NOTE 4) TOP VIE W (P INS DO WN) ...
Page 52
... Royalty for use of the 3rd party IPs may also be payable by users Part Number Ambient Temperature Range °C ADSP-21364SKBCZENG ADSP-21364SKBC-ENG ADSP-21364SKSQZENG ADSP-21364SKSQ-ENG ADSP-21364SBBCZENG – ADSP-21364SBBC-ENG – ADSP-21364SBSQZENG – ADSP-21364SBSQ-ENG – ADSP-21364SCSQZENG –40 to 105 5 ADSP-21364SCSQ-ENG – ...