ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 22

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21364
Timer WDTH_CAP Timing
The following timing specification applies to Timer0, Timer1,
and Timer2 in WDTH_CAP (pulse width count and capture)
mode. Timer signals are routed to the DAI_P20–1 pins through
the SRU. Therefore, the timing specifications provided below
are valid at the DAI_P20–1 pins.
Table 16. Timer Width Capture Timing
DAI Pin to Pin Direct Routing
For direct pin connections only (for example DAI_PB01_I to
DAI_PB02_O).
Table 17. DAI Pin to Pin Routing
Parameter
Timing Requirement
t
Parameter
Timing Requirement
t
PWI
DPIO
Timer Pulse Width
Delay DAI Pin Input Valid to DAI Output Valid
(TIMER2-0)
DAI_P20-1
DAI_PM
DAI_PN
Rev. PrB | Page 22 of 52 | September 2004
Figure 13. Timer Width Capture Timing
Figure 14. DAI Pin to PIN Direct Routing
Min
2 t
PCLK
t
DPIO
t
PWI
Min
1.5
Max
2(2
31
– 1) t
Preliminary Technical Data
PCLK
Max
10
Unit
ns
Unit
ns