ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 40

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21364
SPI Interface—Master
Table 36. SPI Interface Protocol — Master Switching and Timing Specifications
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
SSPIDM
HSPIDM
SPICLKM
SPICHM
SPICLM
DDSPIDM
HDSPIDM
SDSCIM
HDSM
SPITDM
CPHASE=1
CPHASE=0
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
FLAG3-0
(CP = 0)
(CP = 1)
SPICLK
SPICLK
MOSI
(INPUT)
MOSI
(INPUT)
MISO
MISO
t
Data Input Valid to SPICLK Edge (Data Input Set-up Time)
SPICLK Last Sampling Edge to Data Input Not Valid
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
FLAG3–0IN (SPI Device Select) Low to First SPICLK Edge
Last SPICLK edge to FLAG3–0IN High
Sequential Transfer Delay
S S P ID M
t
S D S C I M
VALID
MSB
t
t
MSB
S P I C H M
S P I C L M
VALID
MSB
t
H S P I D M
t
t
D D S P I D M
t
S S P I D M
t
MSB
S P I C L M
S P I C H M
Rev. PrB | Page 40 of 52 | September 2004
t
D D S P I D M
Figure 33. SPI Master Timing
t
H S S P I D M
t
H D S P I D M
t
t
S S P ID M
HDSPIDM
t
VALID
S P I C L K M
LSB
LSB
VALID
LSB
Min
8
2
8 × t
4 × t
4 × t
2
4 × t
4 × t
4 × t
t
H D S M
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
Preliminary Technical Data
LSB
– 2
– 2
– 1
– 1
t
H S P I D M
t
S P I TD M
Max
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns