ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 20

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21364
Reset
Table 12. Reset
1
Interrupts
The following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts. Also applies to DAI_P20–1 pins
when configured as interrupts
Table 13. Interrupts
Parameter
Timing Requirements
t
t
Parameter
Timing Requirement
t
Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 µs while RESET is low, assuming
WRST
SRST
IPW
stable VDD and CLKIN (not including start-up time of external clock oscillator).
1
RESET Pulse Width Low
RESET Setup Before CLKIN Low
IRQx Pulse Width
CLKIN
RESET
DAI_P20-1
FLAG2-0
(IRQ2-0)
Rev. PrB | Page 20 of 52 | September 2004
Figure 10. Interrupts
Figure 9. Reset
t
t
IPW
WRST
Min
4t
8
CK
Min
2 × t
PCLK
+ 2
Max
Preliminary Technical Data
t
SRST
Max
Unit
ns
ns
Unit
ns