ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 37

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
SPDIF Transmitter Input Data Timing
The timing requirements for the Input port are given in
Table
DAI_P20–1 pins using the SRU. Therefore, the timing specifica-
tions provided below are valid at the DAI_P20–1 pins.
Table 32. SPDIF Transmitter Input Data Timing
1
Over Sampling Clock (TXCLK) Switching Characteristics
SPDIF Transmitter has an over sampling clock. This TXCLK
input is divided down to generate the Biphase Clock.
Table 33. Over Sampling Clock (TXCLK) Switching Characteristics
Parameter
Timing Requirements
t
t
t
t
t
t
Parameter
TXCLK Frequency for TXCLK = 768 × FS
TXCLK Frequency for TXCLK = 512 × FS
TXCLK Frequency for TXCLK = 384 × FS
TXCLK Frequency for TXCLK = 256 × FS
Frame Rate
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
SIFS
SIHFS
SISD
SIHD
SISCLKW
SISCLK
1
1
1
1
32. Input Signals (SCLK, FS, SDATA) are routed to the
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SData Setup Before SCLK Rising Edge
SData Hold After SCLK Rising Edge
Clock Width
Clock Period
DAI_P20-1
DAI_P20-1
DAI_P20-1
(SDATA)
(SCLK)
(FS)
Rev. PrB | Page 37 of 52 | September 2004
Figure 30. SPDIF Transmitter Input Timing
t
SISCLKW
t
SISFS
t
SISD
SAMPLE EDGE
Min
4
5.5
4
5.5
9
20
Min
t
t
SIHFS
SIH D
Max
Max
147.5
98.4
73.8
49.2
192.0
ADSP-21364
Unit
ns
ns
ns
ns
ns
ns
Unit
MHz
MHz
MHz
MHz
MHz