ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 34

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21364
Sample Rate Converter—Serial Input Port
The SRC input signals (SCLK, FS, and SDATA) are routed from
the DAI_P20–1 pins using the SRU. Therefore, the timing spec-
ifications provided in
Table 30. SRC, Serial Input Port
1
Parameter
Timing Requirements
t
t
t
t
t
t
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
SIFS
SIHFS
SISD
SIHD
IDPCLKW
IDPCLK
1
1
1
1
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
SData Setup Before SCLK Rising Edge
SData Hold After SCLK Rising Edge
Clock Width
Clock Period
Table 30
are valid at the DAI_P20–1 pins.
DAI_P20-1
DAI_P20-1
DAI_P20-1
(SDATA)
(SCLK)
(FS)
Rev. PrB | Page 34 of 52 | September 2004
Figure 25. SRC Serial Input Port Timing
t
IDPCLKW
t
SISFS
t
SISD
SAMPLE EDGE
Min
4
5.5
4
5.5
9
20
Preliminary Technical Data
t
t
SIHFS
SIHD
Max
Unit
ns
ns
ns
ns
ns
ns