ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 21

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Core Timer
The following timing specification applies to FLAG3 when it is
configured as the core timer (CTIMER).
Table 14. Core Timer
Timer PWM_OUT Cycle Timing
The following timing specification applies to Timer0, Timer1,
and Timer2 in PWM_OUT (pulse width modulation) mode.
Timer signals are routed to the DAI_P20–1 pins through the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 15. Timer PWM_OUT Timing
Parameter
Switching Characteristic
t
Parameter
Switching Characteristic
t
WCTIM
PWMO
(CTIMER)
FLAG3
Timer Pulse Width Output
CTIMER Pulse Width
(TIMER2-0)
DAI_P20-1
Rev. PrB | Page 21 of 52 | September 2004
Figure 12. Timer PWM_OUT Timing
Figure 11. Core Timer
Min
2 t
PCLK
Min
4 × t
– 1
PCLK
t
WCTIM
t
PWMO
– 1
Max
2(2
31
– 1) t
Max
PCLK
ADSP-21364
Unit
ns
Unit
ns