ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 36

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21364
SPDIF Transmitter
Serial data input to the SPDIF transmitter can be formatted as
left justified, I
or 24 bits. The following sections provide timing for the
transmitter.
SPDIF Transmitter—Serial Input Waveforms
Figure 27
left channel and LO for the right channel. Data is valid on the
rising edge of SCLK. The MSB is delayed 12-bit clock periods
(in 20-bit output mode) or 16-bit clock periods (in 16-bit output
Figure 28
for the left channel and HI for the right channel. Data is valid on
the rising edge of SCLK. The MSB is left-justified to an LRCLK
transition but with a single SCLK period delay.
Figure 29
channel and LO for the right channel. Data is valid on the rising
edge of SCLK. The MSB is left-justified to an LRCLK transition
with no MSB delay.
SDATA
LRCLK
SCLK
SDATA
LRCLK
SCLK
SDATA
LRCLK
SCLK
shows the left-justified mode. LRCLK is HI for the left
shows the right-justified mode. LRCLK is HI for the
shows the default I2S-justified mode. LRCLK is LO
LSB
2
S or right justified with word widths of 16, 18, 20,
MSB
MSB-1
MSB
MSB-2
MSB-1 MSB-2
MSB
LEFT CHANNEL
LSB+2
LEFT CHANNEL
MSB-1 MSB-2
LSB+1
LSB+2 LSB+1
LEFT CHANNEL
LSB
Rev. PrB | Page 36 of 52 | September 2004
Figure 27. Right-Justified Mode
Figure 29. Left-Justified Mode
LSB
LSB+2 LSB+1
Figure 28. I
LSB
2
S-Justified Mode
MSB
MSB-1
mode) from an LRCLK transition, so that when there are 64
SCLK periods per LRCLK period, the LSB of the data will be
right-justified to the next LRCLK transition.
RIGHT CHANNEL
MSB
MSB-2
MSB-1
MSB-2
RIGHT CHANNEL
RIGHT CHANNEL
MSB
LSB+2
Preliminary Technical Data
MSB-1 MSB-2
LSB+1
LSB+2
LSB
LSB+1
LSB
LSB+2
LSB+1
LSB
MSB
MSB+1
MSB