ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 35

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and it
should meet setup and hold times with regard to SCLK on the
output port. The serial data output, SDATA, has a hold time
Table 31. SRC, Serial Output Port
1
Parameter
Timing Requirements
t
t
t
t
DATA, SCLK, FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG's input can be either CLKIN or any of the DAI pins.
SIFS
SIHFS
SRCTDD
SRCTDH
1
1
1
1
FS Setup Before SCLK Rising Edge
FS Hold Before SCLK Rising Edge
Transmit Data Delay After SCLK Falling Edge
Transmit Data Hold After SCLK Falling Edge
DAI_P20-1
DAI_P20-1
DAI_P20-1
(SDATA)
(SCLK)
(FS)
Rev. PrB | Page 35 of 52 | September 2004
Figure 26. SRC Serial Output Port Timing
t
SRCTDD
t
t
SISCLKW
SR CTDH
t
SIFS
and delay specification with regard to SCLK. Note that SCLK
rising edge is the sampling edge and the falling edge is the drive
edge.
SAMPLE EDGE
Min
4
5.5
2
t
SIHFS
Max
7
ADSP-21364
Unit
ns
ns
ns
ns