ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 4

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21364
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each
processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2136x enhanced Har-
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0–R15 and in PEY as S0–S15.
(OPTIONAL)
(OPTIONAL)
ADC
DAC
CLOCK
SDAT
SDAT
CLK
CLK
FS
FS
2
2
3
CLKIN
XTAL
CLK_CFG1-0
BOOTCFG1-0
FLAG3-1
DAI_P19
DAI_P18
DAI_P20
DAI_P1
DAI_P2
DAI_P3
DAI
RESET
ADSP-21364
SRU
Figure 2. ADSP-21364 System Sample Configuration
CLK
FS
Rev. PrB | Page 4 of 52 | September 2004
PCGA
PCG B
SPORT0-5
SCLK0
SFS0
SD0A
SD0B
TIMERS
SPDI F
SRC
JTAG
IDP
SPI
6
CLKOUT
AD15-0
FLAG0
ALE
WR
RD
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21364 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see
gram and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a sin-
gle cycle.
Instruction Cache
The ADSP-21364 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators With Zero-Overhead Hardware
Circular Buffer Support
The ADSP-21364’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program-
ming of delay lines and other data structures required in digital
Figure 1 on Page
LATCH
Preliminary Technical Data
1). With the ADSP-21364’s separate pro-
CS
ADDR
DATA
OE
WE
PARALLEL
BOO T ROM
I /O DEVI CE
RAM, ROM
PORT