ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 18

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21364
Power-Up Sequencing
The timing requirements for processor startup are given in
Table
Table 10. Power-Up Sequencing Timing Requirements (Processor Startup)
1
2
3
4
5
Parameter
Timing Requirements
t
t
t
t
t
Switching Characteristic
t
Valid V
Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to your crystal oscillator manufacturer's datasheet for startup time.
Based on CLKIN cycles
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and
The 4096 cycle count depends on t
RSTVDD
IVDDEVDD
CLKVDD
CLKRST
PLLRST
CORERST
depending on the design of the power supply subsystem.
Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
propagate default states at all I/O pins.
cycles maximum.
10.
DDINT
1
/V
DDEXT
CLK_CFG1-0
assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
V DDEXT
RSTOUT
V DDINT
RESET
CLKIN
RESET Low Before V
V
CLKIN Valid After V
CLKIN Valid Before RESET Deasserted
PLL Control Setup Before RESET Deasserted
Core Reset Deasserted After RESET Deasserted
DDINT
SRST
on Before V
specification in
t
RSTVDD
DDEXT
DDINT
DDINT
Table
/V
/V
Rev. PrB | Page 18 of 52 | September 2004
DDEXT
t
12. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097
DDEXT
IVDDEVDD
Figure 6. Power Up Sequencing
Valid
on
t
CLKVDD
t
PLLRST
t
CLKRST
t
CORERST
Min
0
–50
0
10
20
4096t
2
3
Preliminary Technical Data
CK
+ 2 t
CCLK
4, 5
Max
200
200
Unit
ns
ms
ms
µs
µs