ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 14

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21364
ADDRESS DATA PINS AS FLAGS
To use these pins as flags (FLAGS15–0) set (=1) bit 20 of the
SYSCTL register to disable the parallel port. Then set (=1) bits
22 to 25 in the SYSCTL register accordingly.
Table 4. AD15–0 to Flag Pin Mapping
ADDRESS DATA MODES
The following table shows the functionality of the AD pins for
8-bit and 16-bit transfers to the parallel port. For 8-bit data
transfers, ALE latches address bits A23–A8 when asserted, fol-
lowed by address bits A7–A0 and data bits D7–D0 when
deasserted. For 16-bit data transfers, ALE latches address bits
A15–A0 when asserted, followed by data bits D15–D0 when
deasserted.
Table 5. Address/ Data Mode Selection
AD Pin
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
EP Data
Mode
8-bit
8-bit
16-bit
16-bit
ALE
Asserted
Deasserted
Asserted
Deasserted
Flag Pin
FLAG8
FLAG9
FLAG10
FLAG11
FLAG12
FLAG13
FLAG14
FLAG15
AD Pin
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD7–0
Function
A15–8
D7–0
A7–0
D7–0
Flag Pin
FLAG0
FLAG1
FLAG2
FLAG3
FLAG4
FLAG5
FLAG6
FLAG7
Rev. PrB | Page 14 of 52 | September 2004
D15–8
AD15–8
Function
A23–16
A7–0
A15–8
BOOT MODES
Table 6. Boot Mode Selection
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
For details on processor timing, see
Figure 5 on Page
Table 7. Core Instruction Rate/ CLKIN Ratio Selection
BOOTCFG1–0
00
01
10
CLKCFG1–0
00
01
10
17.
Preliminary Technical Data
Booting Mode
SPI Slave Boot
SPI Master Boot
Parallel Port boot via EPROM
Core to CLKIN Ratio
6:1
32:1
16:1
Timing Specifications
and