ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 27

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Memory Write—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the
ADSP-21364 is accessing external memory space.
Table 22. 8-bit Memory Write Cycle
1
Parameter
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
t
D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t
H = t
F = 7 x t
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
ALEW
ADAS
ALERW
RWALE
WRH
ADAH
WW
ADWL
ADWH
DWS
DWH
DAWH
PCLK
1
1
PCLK
(if a hold cycle is specified, else H = 0)
(if FLASH_MODE is set else F = 0)
AD15-8
AD7-0
ALE Pulse Width
Address/Data 15–0 Setup Before ALE Deasserted
ALE Deasserted to Read/Write Asserted
Write Deasserted to ALE Asserted
Delay Between WR Rising Edge to next WR Falling Edge
Address/Data 15–0 Hold After ALE Deasserted
WR Pulse Width
Address/Data 15–8 to WR Low
Address/Data 15–8 Hold After WR High
Address/Data 7–0 Setup Before WR High
Address/Data 7–0 Hold After WR High
Address/Data to WR High
ALE
WR
RD
t
ALEW
t
ADAS
ADDRESS
ADDRESS
Figure 19. Write Cycle For 8-Bit Memory Timing
VALID
VALID
Rev. PrB | Page 27 of 52 | September 2004
t
t
ADAH
ADWL
t
ALERW
VALID ADDRESS
VALID DATA
t
t
DAWH
DWS
t
WW
t
WRH
VALID ADDRESS
t
t
VALID DATA
ADWH
DWH
Min
2 × t
t
2 × t
H + 0.5
F + H + t
t
D – F – 2
t
H
D – F + t
H
D – F + t
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
– 2.5
– 0.5
– 1.5
t
RWALE
PCLK
PCLK
PCLK
– 2
– 2
– 4
– 4
– 2
Max
ADSP-21364
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns