ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 38

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21364
SPDIF Receiver
The following sections describe timing as it relates to the SPDIF
receiver.
Internal Digital PLL Mode
In internal Digital Phase-locked Loop mode the internal PLL
(Digital PLL) generates the 512
Table 34. SPDIF Receiver Internal Digital PLL Mode Timing
1
Parameter
Switching Characteristics
t
t
t
t
t
t
SCLK frequency is 64 x FS where FS = the frequency of LRCLK.
DFSI
HOFSI
DDTI
HDTI
SCLKIW
CCLK
1
LRCLK Delay After SCLK
LRCLK Hold After SCLK
Transmit Data Delay After SCLK
Transmit Data Hold After SCLK
Transmit SCLK Width
Core Clock Period
× Fs clock.
(DATA CHANNEL A/B)
DAI_P20-1
Figure 31. SPDIF Receiver Internal Digital PLL Mode Timing
DAI_P20-1
DAI_P20-1
(SCLK)
(FS)
Rev. PrB | Page 38 of 52 | September 2004
DRIVE EDGE
t
t
HOFSI
HDTI
t
DFSI
t
SCLKIW
t
DDTI
Min
–2
–2
40
t
SFSI
SAMPLE EDGE
Max
5
5
5
t
Preliminary Technical Data
HFSI
Unit
ns
ns
ns
ns
ns
ns