ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 42

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ADSP-21364SBBCZENG

Manufacturer Part Number
ADSP-21364SBBCZENG
Description
SHARC Processor
Manufacturer
AD [Analog Devices]
Datasheet
ADSP-21364
JTAG Test Access Port and Emulation
Table 38. JTAG Test Access Port and Emulation
1
2
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
System Inputs = AD15–0, SPIDS, CLKCFG1–0, RESET, BOOTCFG1–0, MISO, MOSI, SPICLK, DAI_Px, FLAG3–0.
System Outputs = MISO, MOSI, SPICLK, DAI_Px, AD15–0, RD, WR, FLAG3–0, CLKOUT, EMU, ALE.
TCK
STAP
HTAP
SSYS
HSYS
TRSTW
DTDO
DSYS
1
1
2
TCK Period
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
System Inputs Setup Before TCK Low
System Inputs Hold After TCK Low
TRST Pulse Width
TDO Delay From TCK Low
System Outputs Delay After TCK Low
SYSTEM
OUTPUTS
SYSTEM
INPUTS
TCK
TMS
TDI
TDO
t
DTDO
Figure 35. IEEE 1149.1 JTAG Test Access Port
Rev. PrB | Page 42 of 52 | September 2004
t
TCK
t
DSYS
t
STAP
t
HTAP
Min
t
5
6
7
18
4t
CK
CK
t
SSYS
Preliminary Technical Data
Max
7
10
t
HSYS
Unit
ns
ns
ns
ns
ns
ns
ns
ns

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