ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 25

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Memory Read—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the
ADSP-21364 is accessing external memory space.
Table 20. 8-Bit Memory Read Cycle
1
Parameter
Timing Requirements
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
D = (Data Cycle Duration = the value set by the PPDUR bits (5–1) in the PPCTL register) × t
H = t
F = 7 x t
t
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
DRS
DRH
DAD
ALEW
ADAS
RRH
ALERW
RWALE
ADAH
ALEHZ
RW
RDDRV
ADRH
PCLK
PCLK
1
1
= (Peripheral) Clock Period = 2 × t
1
PCLK
(if a hold cycle is specified, else H = 0)
(if FLASH_MODE is set else F = 0)
Address/Data 7–0 Setup Before RD High
Address/Data 7–0 Hold After RD High
Address 15–8 to Data Valid
ALE Pulse Width
Address/Data 15–0 Setup Before ALE Deasserted
Delay Between RD Rising Edge to Next Falling Edge.
ALE Deasserted to Read Asserted
Read Deasserted to ALE Asserted
Address/Data 15–0 Hold After ALE Deasserted
ALE Deasserted to Address/Data7–0 in High Z
RD Pulse Width
RD Address Drive After Read High
Address/Data 15–8 Hold After RD High
AD15-8
AD7-0
ALE
WR
RD
CCLK
t
t
ALEW
ADAS
VALID ADDRESS
VALID ADDRESS
Figure 17. Read Cycle For 8-Bit Memory Timing
Rev. PrB | Page 25 of 52 | September 2004
t
ADAH
t
ALEHZ
t
ALERW
VALID ADDRESS
t
RW
VALID
DATA
t
t
Min
3.3
0
2 × t
H + t
2 × t
F + H + 0.5
t
D – 2
F + H + t
H
PCLK
PCLK
PCLK
t
RRH
PCLK
PCLK
PCLK
t
– 2.5
– 0.8
– 0.8
DAD
VALID ADDRESS
PCLK
– 2.0
– 2
– 1
t
DRS
PCLK
– 1
t
RWALE
VALID
DATA
t
ADRH
t
DRH
t
RDDRV
ADDRESS
ADDRESS
VALID
VALID
Max
D + t
t
PCLK
PCLK
– 5
ADSP-21364
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns