ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 39

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
External PLL Mode
In External PLL Mode internal Digital PLL is disabled and the
receiver runs on the PLL that is connected to the processor
externally. This external PLL generates the 512 x Fs clock
(MCLK) from the reference clock (LRCLK) and gives it to
SPDIF receiver.
Table 35. SPDIF Receiver External PLL Mode Timing
Parameter
Timing Requirements
t
FMCLK
t
t
t
t
t
MCP
BDM
LDM
DDP
DDS
DDH
RIGHT-JUSTIFIED
SDATA OUTPUT
(NOT TO SCALE)
SDATA OUTPUT
I 2 S-JUSTIFIED
MCLK INPUT
BCLK OUTPUT
MODE
MODE
OUTPUT
LRCLK
MCLK Period
MCLK Frequency (1/t
SCLK Propagation Delay from MCLK to the Falling Edge
LRCLK Propagation Delay From MCLK
Data Propagation Delay From MCLK
Data Output Setup To SCLK
Data Output Hold From SCLK
t
t
BDM
LDM
Figure 32. SPDIF Receiver External PLL Mode Timing
t
DDP
MCP
Rev. PrB | Page 39 of 52 | September 2004
MSB
)
t
DDH
t
DDS
t
DDP
t
DDS
MSB
t
DDH
Min
10
1/2 SCLK Period
1/2 SCLK Period
t
DDS
LSB
Max
100
30
30
30
t
DDH
ADSP-21364
Unit
ns
MHz
ns
ns
ns
ns
ns