ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 30

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21364
Table 26. Serial Ports—Enable and Three-State
1
Table 27. Serial Ports—External Late Frame Sync
1
1
Parameter
Switching Characteristics
t
t
t
Parameter
Switching Characteristics
t
t
Referenced to drive edge.
The t
This figure reflects changes made to support Left-justified Sample Pair mode.
DDTEN
DDTTE
DDTIN
DDTLFSE
DDTENFS
DDTLFSE
1
1
1
1
1
and t
DDTENFS
Data Enable from External Transmit SCLK
Data Disable from External Transmit SCLK
Data Enable from Internal Transmit SCLK
Data Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 0
Data Enable for MCE = 1, MFD = 0
parameters apply to Left-justified Sample Pair as well as DSP serial mode, and MCE = 1, MFD = 0.
(DATA CHANNEL A/B)
(DATA CHANNEL A/B)
DAI_P20-1
DAI_P20-1
DAI_P20-1
NOTE
SERIAL PORT SIGNALS (SCLK, FS,
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P20-1 PINS.
DAI_P20-1
DAI_P20-1
DAI_P20-1
(SCLK)
(SCLK)
(FS)
(FS)
DRIVE
DRIVE
Rev. PrB | Page 30 of 52 | September 2004
t
DDTLFSE
1
t
Figure 21. External Late Frame Sync
DDTLFSE
t
t
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
SFSE/I
SFSE/I
t
LATE EXTERNAL TRANSMIT FS
DDTENFS
t
DDTENFS
DATA CHANNEL
SAMPLE
SAMPLE
1ST BIT
1ST BIT
t
HDTE/I
t
HDTE/I
A/B) ARE ROUTED TO THE DAI_P20-1 PINS
DRIVE
DRIVE
t
HFSE/I
t
HFSE/I
1
2
Min
–1
Min
0.5
t
DDTE/I
t
DDTE/I
Preliminary Technical Data
2ND BIT
2ND BIT
Max
7
Max
7
Unit
ns
ns
ns
Unit
ns
ns