ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 2

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

ADSP-21364
KEY FEATURES – PROCESSOR CORE
At 333 MHz (3.0 ns) core instruction rate, the ADSP-21364
3M bit on-chip single-ported SRAM (1M Bit in blocks 0 and 1,
4M bit on-chip single-ported mask-programmable ROM (2M
Zero-overhead looping with single-cycle loop setup, provid-
Single Instruction Multiple Data (SIMD) architecture
Transfers between memory and core at a sustained 5.4
INPUT/OUTPUT FEATURES
DMA Controller supports:
25 DMA channels for transfers between ADSP-21364 internal
32-bit DMA transfers at core clock speed, in parallel with full-
Asynchronous parallel port provides access to asynchronous
16 multiplexed address/data lines support 24-bit address
External memory access in a dedicated DMA channel
8- to 32- bit and 16- to 32-bit packing options
Programmable data cycle duration: 2 to 31 CCLK
Digital audio interface (DAI) includes six serial ports, two Pre-
Six dual data line serial ports that operate at up to 50M bit/s
Left-justified Sample Pair and I
TDM support for telecommunications interfaces including
performs 2 GFLOPS/666 MMACS
and 0.50M Bit in blocks 2 and 3) for simultaneous access by
core processor and DMA
bit in block 0 and 2M bit in block 1)
Dual Data Address Generators (DAGs) with modulo and
bit-reverse addressing
ing efficient program sequencing
provides:
Two computational processing elements
Concurrent execution
Code compatibility with other SHARC family members at
Parallelism in busses and computational units allows sin-
Gbytes/s bandwidth at 333 MHz core instruction rate
memory a variety of peripherals
speed processor execution
external memory
external address range with 8-bit data or 16-bit address
external address range with 16-bit data
55 Mbyte per sec transfer rate
cision Clock Generators, an Input Data Port, three timers,
eight-channel asynchronous sample rate converter, and a
Signal routing unit
on each data line—each has a clock, frame sync and two
data lines that can be configured as either a receiver or
transmitter pair
direction for up to 24 simultaneous receive or transmit
channels using two I
port
128 TDM channel support for newer telephony interfaces
such as H.100/H.110
the assembly level
gle cycle execution (with or without SIMD) of a multiply
or ALU operation, a dual memory read or write, and an
instruction fetch
2
S compatible stereo devices per serial
2
S Support, programmable
Rev. PrB | Page 2 of 52 | September 2004
Up to 12 TDM stream support, each with 128 channels per
Companding selection on a per channel basis in TDM mode
Input data port provides an additional input path to the
Signal routing unit provides configurable and flexible con-
Two Serial Peripheral Interfaces (SPI): primary on dedicated
3 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired line
DEDICATED AUDIO COMPONENTS
S/PDIF Compatible Digital Audio receiver/transmitter
Sample Rate Converter (SRC) Contains a Serial Input Port, De-
Pulse Width Modulation provides:
PLL has a wide variety of software and hardware multi-
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball Mini-BGA and 144-lead LQFP Packages
frame
SHARC core, configurable as eight channels of serial data
or seven channels of serial data and a single channel of up
to 20-bit wide parallel data
nections between all DAI components–six serial ports, two
precision clock generators, an input data port with a data
acquisition port, one SPI port, eight channels of asynchro-
nous sample rate converters, three timers, 10 interrupts,
six flag inputs, six flag outputs, and 20 SRU I/O pins
(DAI_Px)
pins, secondary on DAI pins provide:
Master or slave serial boot through primary SPI
Full-duplex operation
Master-Slave mode multi-master support
Open drain outputs
Programmable baud rates, clock polarities and phases
supports:
EIAJ CP-340 (CP-1201), IEC-958, AES/EBU standards
Left justified, I
18, 20 or 24 bit word widths (transmitter)
Two channel mode and Single Channel Double Frequency
(SCDF) mode
emphasis Filter providing up to -140db SNR performance,
Sample Rate Converter (SRC) and Serial Output Port
Supports Left Justified, I
18 and 16 bit serial formats (input)
16 PWM outputs configured as four groups of four outputs
Supports center-aligned or edge-aligned PWM waveforms
Can generate complementary signals on two outputs in
paired mode or independent signals in nonpaired mode
plier/divider ratios
2
Preliminary Technical Data
S or right justified serial data input with 16,
2
S, TDM and Right Justified 24, 20,