ADSP-21364SBBCZENG AD [Analog Devices], ADSP-21364SBBCZENG Datasheet - Page 19

• Manufacturer Part Number: ADSP-21364SBBCZENG
• Description: SHARC Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
Clock Input
Table 11. Clock Input
1
2
3
Clock Signals
The ADSP-21364 can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-21364 to use its internal clock generator by connecting
the necessary components to CLKIN and XTAL.
the component connections used for a crystal operating in fun-
damental mode. Note that the clock rate is achieved using a
16.67 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN achieves a clock speed of 266 MHz). To achieve
the full core clock rate, programs need to configure the multi-
plier bits in the PMCTL register.
Parameter
Timing Requirements
t
t
t
t
t
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CK
CKL
CKH
CKRF
CCLK
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.
CLKIN
3
Figure 8. 333 MHz Operation (Fundamental Mode Crystal)
C1
CLKIN
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4V–2.0V)
CCLK Period
1M
X1
Figure 7. Clock Input
t
CKH
C2
XTAL
t
CK
t
CKL
Rev. PrB | Page 19 of 52 | September 2004
Figure 8
shows
Min
18
7.5
7.5
3.0
1
1
1
1
CCLK
.
333 MHz
Max
TBD
TBD
TBD
TBD
TBD
2
2
2
Unit
ns
ns
ns
ns
ns
ADSP-21364