DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 151

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DS3181/DS3182/DS3183/DS3184
10.8.3 Transmit PLCP Frame Processor
The Transmit PLCP Frame Processor receives the ATM cells from the ATM/Packet Processor performs trailer
generation, framing generation, error insertion, and overhead insertion.
The bits in a byte are transmitted MSB first, LSB last. When they are input serially, they are input in the order they
are to be transmitted. The bits in a byte in an outgoing signal are numbered in the order they are transmitted, 1
(MSB) to 8 (LSB). However, when a byte is stored in a register, the MSB is stored in the highest numbered bit (7),
and the LSB is stored in the lowest numbered bit (0). This is to differentiate between a byte in a register and the
corresponding byte in a signal.
10.8.4 Receive PLCP Frame Processor
The Receive PLCP Frame Processor accepts the data stream from the DS3/E3 Framer and extracts the entire
DS3/E3 overhead and processes only the PLCP frame data.
The bits in a byte are received MSB first, LSB last. When they are output serially, they are output in the order they
are received. The bits in a byte in an incoming signal are numbered in the order they are received, 1 (MSB) to 8
(LSB). However, when a byte is stored in a register, the MSB is stored in the highest numbered bit (7), and the LSB
is stored in the lowest numbered bit (0). This is to differentiate between a byte in a register and the corresponding
byte in a signal.
Some bits, bit groups, or bytes (data) are integrated. Integration requires the data to have a new value for five
consecutive occurrences before the new data value will be stored in the data register. Integrated data may have an
associated unstable indication. Integrated data is considered unstable if for eight consecutive occurrences the
received data value does not match the currently stored (integrated) data value or the previously received data
value.
10.8.5 Transmit DS3 PLCP Frame Processor
The DS3 PLCP frame format is shown in
Figure
10-32. A1 and A2 are the sub-frame alignment bytes that have a
value of F6h and 28h respectively. P11 – P0 are the Path Overhead Identifier (POI) bytes that indicate the path
overhead byte contained in the current sub-frame. Z6 – Z1 are growth bytes reserved for future use. F1 is the Path
User Channel byte allocated for user communications purposes (This byte is undefined in ATM). B1 is the Bit
Interleaved Parity-8 (BIP-8) byte used for PLCP path error monitoring. G1 is the PLCP Path Status Byte (See
Figure
10-33) used for far-end path status and performance monitoring (bits 6 – 8 are undefined in ATM). M2 and
M1 are the DQDB Layer Management Information bytes used for DQDB layer management communications
(These bytes are undefined in ATM). C1 is the Cycle/Stuff Counter byte used as for PLCP superframe alignment
and stuff indication.
151