DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 248

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DS3184DK

Manufacturer Part Number
DS3184DK
Description
KIT DEMO FOR DS3184
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3184DK

Main Purpose
Telecom, ATM / Packet PHYs
Utilized Ic / Part
DS3184
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 3: Performance Monitoring Update Status Interrupt Enable (PMSIE) – This bit enables an interrupt if the
PMSL bit is set.
Bit 2: Bit Error Interrupt Enable (BEIE) – This bit enables an interrupt if the BEL bit is set and the bit in
GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 1: Bit Error Count Interrupt Enable (BECIE) – This bit enables an interrupt if the BECL bit is set and the bit in
GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 0: Out Of Synchronization Interrupt Enable (OOSIE) – This bit enables an interrupt if the OOSL bit is set and
the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
15
0
7
0
14
0
6
0
BERT.SRIE
BERT Status Register Interrupt Enable
(0,2,4,6)70h
13
0
5
0
12
0
0
4
248
PMSIE
11
0
3
0
BEIE
10
0
2
0
BECIE
9
0
1
0
OOSIE
8
0
0
0

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