DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 170

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The bit C
The bits C
The bits C
generated automatically or inserted from a register bit. The FEBE bit source is programmable (automatic or
register). If the T3.TCR.AFEBED register bit is one then the T3.TCR.TFEBE register bit controls this bit. If the
FEBE bit is generated automatically, it is zero when at least one C-bit parity error has been detected during the
previous frame.
The bits C
Once all of the DS3 overhead bits have been overwritten, the data stream is passed on to error insertion. If frame
generation is disabled, the incoming DS3 signal is passed on to error insertion. Frame generation is programmable
(on or off). Note: P-bit generation may still be performed even if frame generation is disabled.
10.10.5.3 Transmit C-bit DS3 Error Insertion
Error insertion inserts various types of errors into the different DS3 overhead bits. The types of errors that can be
inserted are framing errors, P-bit parity errors, C-bit parity errors, and Far-End Block Error (FEBE) errors.
The framing error insertion mode is programmable (F-bit, M-bit, SEF, or OOMF). An F-bit error is a single sub-
frame alignment bit (F
error is an error in all the sub-frame alignment bits in a sub-frame (F
single multiframe alignment bit (M
A P-bit parity error is generated by is inverting the value of the P-bits (P
error(s) can be inserted one error at a time, or continuously. The P-bit parity error insertion mode (single or
continuous) is programmable.
A C-bit parity error is generated by is inverting the value of the C
parity error(s) can be inserted one error at a time, or continuously. The C-bit parity error insertion mode (single or
continuous) is programmable.
A FEBE error is generated by forcing the C
inserted one error at a time, or continuously. The FEBE error insertion rate (single or continuous) is programmable.
Each error type (framing, P-bit parity, C-bit parity, or FEBE) has a separate enable. Continuous error insertion
mode inserts errors at every opportunity. Single error insertion mode inserts an error at the next opportunity when
requested. The framing multi-error modes (SEF or OOMF) insert the indicated number of error(s) at the next
opportunities when requested; i.e., a single request will cause multiple errors to be inserted. The requests can be
initiated by a register bit (TSEI) or by the manual error insertion input (TMEI). The error insertion initiation type
(register or input) is programmable. The insertion of each particular error type is individually enabled. Once all error
insertion has been performed, the data stream is passed on to overhead insertion.
10.10.5.4 Transmit C-bit DS3 Overhead Insertion
Overhead insertion can insert any (or all) of the DS3 overhead bits into the DS3 frame. The DS3 overhead bits X
X
TOHSOFn). The P-bits (P
the input bit and the internally generated bit). The DS3 overhead insertion is fully controlled by the transmit
overhead interface. If the transmit overhead data enable signal (TOHENn) is driven high, then the bit on the
transmit overhead signal (TOHn) is inserted into the output data stream. Insertion of bits using the TOHn signal
overwrites internal overhead insertion.
10.10.5.5 Transmit C-bit DS3 AIS/Idle Generation
C-bit DS3 AIS/Idle generation overwrites the data stream with AIS or an Idle signal. If transmit Idle is enabled, the
data stream payload is forced to an 1100 pattern with two ones immediately following each DS3 overhead bit. M
M
overwritten with the values one, zero, zero, and one (1001) respectively. X
P
If transmit AIS is enabled, the data stream payload is forced to a 1010 pattern with a one immediately following
each DS3 overhead bit. M
F
X1
2
1
2
, P
, P
, and M
, F
1
2,
, P
X2
C
, F
31
2
13
, M
, C
31
51
3
X3
41
is overwritten with the Far-End Alarm and Control (FEAC) data input from the transmit FEAC controller.
bits are overwritten with the values zero, one, and zero (010) respectively. F
, C
, C
, and F
X
, C
32
, F
, and C
32
52
42
XY
, and C
, and C
, and C
, and C
X4
33
bits are overwritten with the values one, zero, zero, and one (1001) respectively. X
XY
33
53
are overwritten with the calculated payload parity from the previous output DS3 frame.
) error. An M-bit error is a single multiframe alignment bit (M
XY
are all overwritten with the calculated payload parity from the previous DS3 frame.
are overwritten with the path maintenance data link input from the HDLC controller.
43
1
1
, M
and P
can be sourced from the transmit overhead interface (TOHCLKn, TOHn, TOHENn, and
are all overwritten with the Far-End Block Error (FEBE) bit. The FEBE bit can be
2
, and M
1
2
, M
) and C
2
, or M
3
bits are overwritten with the values zero, one, and zero (010) respectively.
31
41
, C
3
, C
) error in two consecutive DS3 frames.
32
42
, and C
, and C
170
33
43
bits are received as an error mask (modulo 2 addition of
bits in a single multiframe to zero. FEBE error(s) can be
31
, C
32
X1
1
, and C
, F
and P
X2
1
, F
and X
2
) in a single DS3 frame. P-bit parity
33
X3
bits in a single DS3 frame. C-bit
, and F
2
are overwritten with 11. And,
1
X1
, M
, F
X4
2
). An OOMF error is a
X2
, or M
, F
X3
, and F
3
) error. An SEF
X4
1
bits are
and X
1
1
2
,
,