DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 188

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.13 FEAC Controller
10.13.1 General Description
The FEAC Controller demaps FEAC codewords from a DS3/E3 data stream in the receive direction and maps
FEAC codewords into a DS3/E3 data stream in the transmit direction. The transmit direction demaps FEAC
codewords from a DS3/E3 data stream.
The receive direction performs FEAC processing, and stores the codewords in the FIFO using line timing. It
removes the codewords from the FIFO and outputs them to the microprocessor via the register interface.
The transmit direction inputs codewords from the microprocessor via the register interface and stores the
codewords. It removes the codewords and performs FEAC processing. See
FEAC Controller in the block diagram
Figure 10-49. FEAC Controller Block Diagram
10.13.2 Features
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10.13.3 Functional Description
The bits in a code are received MSB first, LSB last. When they are output serially, they are output MSB first, LSB
last. The bits in a code in an incoming signal are numbered in the order they are received, 1 (MSB) to 6 (LSB).
However, when a code is stored in a register, the MSB is stored in the lowest numbered bit (0), and the LSB is
stored in the highest numbered bit (5). This is to differentiate between a code in a register and the corresponding
code in a signal.
10.13.3.1 Transmit Data Storage
The Transmit Data Storage block contains the registers for two FEAC codes (C[1:6]) and controller circuitry for
reading and writing the memory. The Transmit Data Storage receives data from the microprocessor interface, and
stores the data in memory. The Transmit FEAC Processor reads the data from the Transmit Data Storage.
Programmable dual codeword output – The transmit side can be programmed to output a single codeword
ten times, one codeword ten times followed by a second codeword ten times, or a single codeword
continuously.
Four codeword receive FIFO
Fully independent transmit and receive paths
Fully independent Line side and register side timing – The FIFO can be read from or written to at the
register interface side while all line side clocks and signals are inactive, and read from or written to at the line
side while all register interface side clocks and signals are inactive.
Clock Rate
Receive
Transmit
DS3/E3
DS3/E3
Adapter
LIU
LIU
Decoder
Encoder
B3ZS/
B3ZS/
HDB3
HDB3
TUA1
TAIS
IEEE P1149.1
JTAG Test
Access Port
FEAC
DS3 / E3
Framer
DS3 / E3
Transmit
Receive
Formatter
Buffer
Trace
Trail
HDLC
188
GEN
UA1
TX FRAC/
PLCP
RX FRAC/
PLCP
Figure 10-49
Rx Packet
Processor
Processor
Processor
Processor
RX BERT
Tx Packet
TX BERT
Rx Cell
Tx Cell
Microprocessor
Interface
for the location of the
FIFO
FIFO
Tx
Rx