DS3184DK Maxim Integrated Products, DS3184DK Datasheet - Page 274

• Manufacturer Part Number: DS3184DK
• Description: KIT DEMO FOR DS3184
• Manufacturer: Maxim Integrated Products

Specifications of DS3184DK

• Main Purpose: Telecom, ATM / Packet PHYs
• Utilized Ic / Part: DS3184
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 3: Receive Trail Trace Identifier Change Latched (RTICL) – This bit is set when the receive trail trace
identifier is updated.
Bit 2: Receive Trail Trace Identifier Mismatch Latched (RTIML) – This bit is set when the TT.RSR.RTIM bit
transitions from 0 to 1.
Bit 1: Receive Trail Trace Identifier Unstable Latched (RTIUL) – This bit is set when the TT.RSR.RTIU bit
transitions from 0 to 1.
Bit 0: Receive Trail Trace Identifier Idle Latched (RIDLL) – This bit is set when the TT.RSR.RIDL bit transitions
from 0 to 1.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 3: Receive Trail Trace Identifier Change Interrupt Enable (RTICIE) – This bit enables an interrupt if the
TT.RSRL.RTICL bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 2: Receive Trail Trace Identifier Mismatch Interrupt Enable (RTIMIE) – This bit enables an interrupt if the
TT.RSRL.RTIML bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 1: Receive Trail Trace Identifier Unstable Interrupt Enable (RTIUIE) – This bit enables an interrupt if the
TT.RSRL.RTIUL bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 0: Receive Trail Trace Identifier Idle Interrupt Enable (RIDLIE) – This bit enables an interrupt if the
TT.RSRL.RIDLL bit is set and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
15
15
—
—
—
—
7
0
7
0
14
14
—
—
—
—
6
0
6
0
TT.RSRL
Trail Trace Receive Status Register Latched
(0,2,4,6)F6h
TT.RSRIE
Trail Trace Receive Status Register Interrupt Enable
(0,2,4,6)F8h
13
13
—
—
—
—
5
0
5
0
12
12
—
—
—
—
0
0
4
4
274
RTICIE
RTICL
11
11
—
—
3
0
3
0
RTIMIE
RTIML
10
10
—
—
2
0
2
0
RTIUIE
RTIUL
—
—
9
1
9
0
1
0
RIDLIE
RIDLL
—
—
8
0
8
0
0
0